Modeling and Simulation of Jitter in Phase-Locked Loops

  • Ken Kundert


A methodology is presented for predicting the jitter performance of a PLL using simulation that is both accurate and efficient. The methodology begins by characterizing the noise behavior of the blocks that make up the PLL using transistor-level simulation. For each block, the jitter is extracted and provided as a parameter to behavioral models for inclusion in a high-level simulation of the entire PLL. This approach is efficient enough to be applied to complex systems, such as frequency synthesizers with large divide ratios or fractional-N synthesizers.


Phase Noise Charge Pump Flicker Noise Loop Filter Frequency Synthesizer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Ken Kundert
    • 1
  1. 1.Cadence Design SystemsSan JoseUSA

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