Evaluation of an Integrated High-Level Synthesis Method

  • P. Arató
  • I. Jankovits
  • Z. Sugár
  • Sz. Szigeti


Benchmarking in High-Level Synthesis is one of the most critical points nowadays. Since several synthesis and data path allocation methods are published, the comparison between these methods is highly important. The goal of this paper is to summarise the basic steps of the HLS design flow trough the PIPE synthesis tool integrated into the Cadence environment, which has been developed at the Department of Process Control, and to describe some of the most popular HLS benchmarks. This paper also presents the basic definitions of the DFGs elements (functional elements, data connections), which are used as the description of the task. These definitions are indispensable for the correct comparison.


Functional Element Conditional Branch Data Connection Differential Equation Solver Recursive Loop 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Péter Arató, Andrzej Rucinski, Robert Davis, Roy Torbert, Istvân Bires, A High- Level Datapath Synthesis Method for Pipelined Structures, Microelectronics Journal 25, 1994.Google Scholar
  2. [2]
    Péter Arató, A Data-flow Model and Method for Optimizing the Pipeline Restarting Period, Proc. of The Eighth Symposium on Microcomputer and Microprocessor Applications, 1994.Google Scholar
  3. [3]
    Péter Arató, Andrzej Rucinski, Istvan Jankovits,Time Scaled High-Level Synthesis for Pipelined Data-flow Structures, Proceedings of ATW’94.Google Scholar
  4. [4]
    Cheng-Tsung Hwang, Jiahn-Hurng Lee, Yu-Chin Hsu, A Formal Approach to the Scheduling Problem in High Level Synthesis, IEEE Transactions on Computer- Aided Design, Vol. 10. No. 4, April 1991.Google Scholar
  5. [5]
    High-Level VLSI Synthesis, Edited by Raul Camposano & Wayne Wolf, Kulwer Academic Publisher, 1991.Google Scholar
  6. [61.
    Wolfgang Rosenstiel, Heinrich Kramer, Scheduling and Assignment in High Level Synthesis*Google Scholar
  7. [7]
    PISYN- High-Level Synthesis of Application Specific Pipelined Hardware, Albert E. Casavant, Ki Soo Hwang, Kristen N. McNall*Google Scholar
  8. [8]
    Pierre G. Paulin, John P. Knight, Force-directed Scheduling for the Behavioral Synthesis of ASIC’s, IEEE Transactions on Computer-Aided Design, 1989/6.Google Scholar
  9. [9]
    Istvan Jankovits, Tamás Visegrádi, Pipelined execution in multi-user sequential recursive loops, Periodica Politechnika, Accepted.Google Scholar
  10. [10]
    Ivan P. Radivojevic, Forrest Brewer: Analysis of Conditional Resource Sharing using a Guard-based Control Representation, Computer Hardware and Design, October 1994.Google Scholar
  11. [11]
    István Béres, Ph.D. theses, Technical University Budapest.Google Scholar
  12. [12]
    István Jankovits, A Scheduling and Allocation Method Based on a Time-Scaled Algorithm, Proc. of The Eighth Symposium on Microcomputer and Microprocessor Applications, 1994.Google Scholar
  13. [13]
    Gábor Paller, Rafael, an Intelligent, Multi-Target Signal-Flow Compiler, Ph.D. theses, Technical University Budapest.Google Scholar
  14. [14]
    Ivan P. Radivojevic, Forrest Brewer, Symbolic Scheduling Techniques, Computer Hardware and Design, 1994.Google Scholar
  15. [15]
    Alice C. Parker, Kayhan K—c—kcakar, Shiv Prakash, Jen-Pin Weng, Unified System ConstructionGoogle Scholar
  16. [16]
    R. Camposano, R. A. Bergamaschi, C. E. Haynes, M. Payer, S. M. Wu: The IBM High-Level Synthesis SystemGoogle Scholar
  17. [17]
    Yu-Chin Hsu, Youn-Long Lin, High-Level Synthesis in the Theda System*Google Scholar
  18. [18]
    Design Framework II Reference Manual 4.3, March 1994.Google Scholar
  19. [19]
    SKILL Language Reference Manual 4.3, March 1994.Google Scholar
  20. [20]
    Verilog-XL Reference Manual 2.0, March 1994.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • P. Arató
    • 1
  • I. Jankovits
    • 1
  • Z. Sugár
    • 1
  • Sz. Szigeti
    • 1
  1. 1.Department of Process ControlTechnical University of BudapestHungary

Personalised recommendations