Multi-level logic optimization figures prominently in the synthesis of very large integrated circuits. Sections 5.1 to 5.3 briefly review basic approaches in multilevel logic optimization. The main objective of this chapter is to demonstrate the intimate relationship between algorithmic concepts of test generation, the AND/OR reasoning of Chapters 3 and 4 and common notions of logic synthesis. Section 5.6 develops a new approach to multi-level logic optimization based on the methods presented in Chapters 3 and 4.
KeywordsBoolean Network Functional Decomposition Fault List Prime Implicants Logic Optimization
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