A utomatic T est P attern G eneration (ATPG) for combinational circuits has been an active field of research for many years. This chapter introduces the basic algorithmic concepts of deterministic test generation for single stuck-at faults in combinational circuits. Today, combinational ATPG for single stuck-at faults is considered quite mature. Most modern tools are based on the contributions of [Roth66], [Goe181], [FuSh83], [ScTr87] and [Larr89].
KeywordsTest Generation Direct Implication Test Vector Fault Signal Primary Input
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