Instruction-Level Parallelism

  • Rainer Leupers


Exploitation of potential parallelism is obviously a major source of code optimization. This chapter therefore focusses on DSP-specific techniques, which aim at parallelization of generated vertical machine code. In the first part, we consider the area of memory address generation. Address generation for DSPs is strongly related to instruction-level parallelism, because taking into account the DSP-specific address generation hardware permits to maximize potential parallelism. In the second part of this chapter, we focus on exploitation of potential parallelism by code compaction. Code compaction identifies potential parallelism, accordingly arranges RTs in time, and generates executable machine code. We analyze the special demands on compaction techniques for DSPs, and we present a novel exact solution to the problem of local code compaction.


Delay Line Control Step Schedule Length Address Generation Array Reference 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Rainer Leupers
    • 1
  1. 1.Department of Computer ScienceUniversity of DortmundDortmundGermany

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