A Catalog of Timing-Recovery Schemes

  • Jan W. M. Bergmans


This chapter presents a range of timing-recovery schemes in more or less chronological order. The emphasis is on the manner in which timing information is extracted from the incoming signal. We refer back to Chapter 9 for a review of basics of timing recovery, and ahead to Chapter 11 for a treatment of PLLs. Each section of the chapter is devoted to a single category of schemes. An attempt has been made to make these treatments self-contained. The reader is encouraged to skip those sections that are of no concern to him. A selection may be based on the concise overview below, or on the introductions of the sections. To facilitate comparisons between schemes, the same notation is used throughout the chapter, and the same idealized recording channels are used for benchmarking purposes. Timing recovery has been a subject of active research for many years, and a vast array of techniques has evolved. Our coverage in this chapter does include some of the mainstream approaches, but is by no means complete. We recommend [22, 50, 44] and [36, Chapter 15] as starting points for further reading.


Matched Filter Loop Filter Tracking Loop Zero Crossing Symbol Interval 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    M.R. Aaron, `PCM Transmission in the Exchange Plant’, Bell Syst. Tech. J., Vol. 41, pp. 99–141, Jan. 1962.Google Scholar
  2. [2]
    W.L. Abbott and J.M. Cioffi, `Timing Recovery for Adaptive Decision Feedback Equalization of the Magnetic Storage Channel’, Proc. GLOBECOM ‘80, pp. 1794–1799, San Diego, CA, Dec. 2–5, 1990.Google Scholar
  3. [3]
    T. Aboulnasr, M. Hage, B. Sayar and S. Aly, `Characterization of a Symbol Rate Timing Recovery Technique for a 2B 1Q Digital Receiver’, IEEE Trans. Commun., Vol. 42, No. 2/3/4, pp. 1409–1414, Feb./March/April 1994.Google Scholar
  4. [4]
    O. Agazzi, C-P. J. Tzeng, D.G. Messerschmitt and D.A. Hodges, `Timing Recovery in Digital Subscriber Loops’, IEEE Trans. Commun., Vol. 33, pp. 558–569, June 1985.CrossRefGoogle Scholar
  5. [5]
    N.A. D’Andrea and U. Mengali, `A Simulation Study of Clock Recovery in QPSK and 9QPRS Systems’, IEEE Trans. Commun., Vol. 33, No. 10, pp. 1139–1142, Oct. 1985.CrossRefGoogle Scholar
  6. [6]
    N.A. D’Andrea and M. Luise, `Design and Analysis of a Jitter-Free Clock Recovery Scheme for QAM Systems’, IEEE Trans. Commun., Vol. 41, No. 9, pp. 1296–1299, Sept. 1993.zbMATHCrossRefGoogle Scholar
  7. [7]
    J. Armstrong, `Symbol Synchronization Using Baud-Rate Sampling and Data-SequenceDependent Signal Processing’, IEEE Trans. Commun., Vol. 39, No. 1, pp. 127–132, Jan. 1991.CrossRefGoogle Scholar
  8. [8]
    G. Ascheid, M. Oerder, J. Stahl, and H. Meyr, `An All Digital Receiver Architecture for Bandwidth Efficient Transmission at High Data Rates’, IEEE Trans. Commun., Vol. 37, No. 8, pp. 804–813, Aug. 1989.CrossRefGoogle Scholar
  9. [9]
    M. Banu and A.E. Dunlop, `Clock Recovery Circuits with Instantaneous Clocking’, Electron. Lett., Vol. 28, No. 23, pp. 2127–2130, Nov. 5, 1992.CrossRefGoogle Scholar
  10. [10]
    W.R. Bennett, `Statistics of Regenerative Data Transmission’, Bell Syst. Tech. J., Vol. 37, pp. 1501–1542, Nov. 1958.Google Scholar
  11. [11]
    J.W.M. Bergmans and H-W Wong-Lam, ‘A Class of Data-Aided Timing-Recovery Schemes’, IEEE Trans. Commun., Vol. 43, No. 2/3/4, pp. 1819–1827, Feb./March/Apr. 1995.Google Scholar
  12. [12]
    J.W.M. Bergmans, `Efficiency of Data-Aided Timing Recovery Schemes’, IEEE Trans. Inform. Theory, Vol. 41, No. 5, pp. 1397–1408, Sept. 1995.CrossRefGoogle Scholar
  13. [13]
    J.I. Brown, `A Digital Phase and Frequency-Sensitive Detector’, Proc. IEEE, Vol. 59, p. 717, Apr. 1971.CrossRefGoogle Scholar
  14. [14]
    R.D. Cideciyan, F. Dolivo, R. Hermann, W. Hirt and W. Schott, `A PRML System for Digital Magnetic Recording’, IEEE J. Selected Areas Commun., Vol. 10, No. 1, pp. 3856, Jan. 1992.CrossRefGoogle Scholar
  15. [15]
    R.C. den Dulk, `Improved Circuit Implementation of Adaptive Phase Comparators’, Electron. Lett., Vol. 24, No. 10, pp. 180–181, May 12, 1988.Google Scholar
  16. [16]
    R.C. den Dulk, `Digital PLL Lock-Detection Circuit’, Electron. Lett., Vol. 24, No. 14, pp. 880–882, Jul. 1988.CrossRefGoogle Scholar
  17. [17]
    D.L. Duttweiler, `The Jitter Performance of Phase-Locked Loops Extracting Timing from Baseband Data Waveforms’, Bell Syst. Tech. J., Vol. 55, pp. 37–58, Jan. 1976.Google Scholar
  18. [18]
    C.A. Ehrenbard and M.F. Tompsett, ‘A Baud-Rate Line Interface for Two-Wire High-Speed Digital Subscriber Loops’, Proc. GLOBECOM’82, pp. 931–935.Google Scholar
  19. [19]
    J. Eijselendoorn and R.C. Den Dulk, `Improved Phase-Locked Loop Performance with Adaptive Phase Comparators’, IEEE Trans. on Aerospace and Electronic Systems, Vol. 18, No. 3, pp. 323–332, May 1982.CrossRefGoogle Scholar
  20. [20]
    T.T. Fang, `Analysis of Self-Noise in a Fourth-Power Clock Regenerator’, IEEE Trans. Commun., Vol. 39, No. 1, pp. 133–140, Jan. 1991.CrossRefGoogle Scholar
  21. [21]
    L.E. Franks and J.P. Bubrouski, `Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme’, IEEE Trans. Commun., Vol. 22, No. 7, pp. 913–920, Jul. 1974.CrossRefGoogle Scholar
  22. [22]
    L.E. Franks, `Carrier and Bit Synchronization in Data Communication-A Tutorial Review’, IEEE Trans. Commun., Vol. 28, pp. 1107–1121, Aug. 1980.CrossRefGoogle Scholar
  23. [23]
    A. Gabor, `High-Density Recording on Magnetic Tape’, Electronics, Vol. 32, pp. 72–75, Oct. 16, 1959.Google Scholar
  24. [24]
    F.M. Gardner, Phaselock Techniques, 2nd ed. New York: Wiley, 1979.Google Scholar
  25. [25]
    F.M. Gardner, `Charge-Pump Phase-Lock Loops’, IEEE Trans. Commun., Vol. 28, No. 11, pp. 1849–1858, Nov. 1980.CrossRefGoogle Scholar
  26. [26]
    F.M. Gardner, `A BPSK/QPSK Timing-Error Detector for Sampled Receivers’, IEEE Trans. Commun., Vol. 34, No. 5, pp. 423–429, May 1986.CrossRefGoogle Scholar
  27. [27]
    F.M. Gardner, `Demodulator Reference Recovery Techniques Suited for Digital Implementation’, ESA Final Report, ESTEC Contract No. 6847/86/NL/DG, Aug. 1988.Google Scholar
  28. [28]
    R.D. Gitlin and J. Salz, `Timing Recovery in PAM Systems’, Bell Syst. Tech. J., Vol. 50, No. 5, pp. 1645–1669, May-June 1971.Google Scholar
  29. [29]
    N.H. Gottfried, `Low Complexity Viterbi Detector for Magnetic Disc Drives’, IEE Proc.E, Vol. 140, No. 1, pp. 78–80, Jan. 1993.Google Scholar
  30. [30]
    J.C. Haartsen and R.C. Den Dulk, `Improved Circuit Implementation of Adaptive Phase Comparators’, Electron. Lett., Vol. 24, No. 10, pp. 575–576, May 1988.CrossRefGoogle Scholar
  31. [31]
    C.W. Helstrom, Statistical Theory of Signal Detection. Oxford: Pergamon press, 1960.Google Scholar
  32. [32]
    C.R. Hogge, Jr., `A Self Correcting Clock Recovery Circuit’, IEEE J. Lightwave Technol., Vol. 3, No. 6, pp. 1312–1314, Dec. 1985.CrossRefGoogle Scholar
  33. [33]
    A. Jennings and B.R. Clarke, Data-Sequence Selective Timing Recovery for PAM Systems’, IEEE Trans. Commun., Vol. 33, pp. 729–731, Jul. 1985.CrossRefGoogle Scholar
  34. [34]
    M. Kawai, `Smart Optical Receiver With Automatic Decision Threshold Setting and Re-timing Phase Alignment’, IEEE J. Lightwave Technol., Vol. 7, No. 11, pp. 1634–1640, Nov. 1989.CrossRefGoogle Scholar
  35. [35]
    K. Kobayashi, `Simultaneous Adaptive Estimation and Decision Algorithm for Carrier Modulated Data Transmission Systems’, IEEE Trans. Commun. Techn., Vol. 19, pp. 268–280, June 1971.zbMATHCrossRefGoogle Scholar
  36. [36]
    E.A. Lee and D.G. Messerschmitt, Digital Communication. Boston: Kluwer Academic Publishers, 1988.CrossRefGoogle Scholar
  37. [37]
    W.C. Lindsey and C.M. Chie, `A Survey of Digital Phase-Locked Loops’, Proc. IEEE, Vol. 69, pp. 410–431, Apr. 1981.CrossRefGoogle Scholar
  38. [38]
    P. Mallory, `A Maximum Likelihood Bit Synchronizer’, International Telemetring Conf., Proc., IV (1968), pp. 1–16.Google Scholar
  39. [39]
    J.E. Mazo, `Jitter Comparison of Tones Generated by Squaring and by Fourth-Power Circuits’, Bell Syst. Tech. J., Vol. 57, pp. 1489–1498, May-June 1978.Google Scholar
  40. [40]
    J.E. Mazo, `Optimum Sampling Phase of an Infinite Equalizer’, Bell Syst. Tech. J., Vol. 54, pp. 189–201, Jan. 1975.Google Scholar
  41. [41]
    U. Mengali, `Joint Phase and Timing Acquisition in Data-Transmission’, IEEE Trans. Commun., Vol. 25, No. 10, pp. 1174–1185, Oct. 1977.zbMATHCrossRefGoogle Scholar
  42. [42]
    H. Meyr and G. Ascheid, Synchronization in Digital Communications, Volume 1. New York: Wiley, 1990.Google Scholar
  43. [43]
    M. Moeneclaey, `A Comparison of Two Types of Symbol Synchronizers for Which Self-Noise is Absent’, IEEE Trans. Commun., Vol. 31, No. 3, pp. 329–334, March 1983.zbMATHCrossRefGoogle Scholar
  44. [44]
    K.H. Mueller and M. Müller, `Timing Recovery in Digital Synchronous Data Receivers’, IEEE Trans. Commun., Vol. 24, No. 5, pp. 516–531, May 1976.zbMATHCrossRefGoogle Scholar
  45. [45]
    M. Oerder, `Derivation of Gardner’s Timing-Error Detector from the Maximum Likelihood Principle’, IEEE Trans. Commun., Vol. 35, No. 6, pp. 684–685, June 1987.CrossRefGoogle Scholar
  46. [46]
    M. Oerder and H. Meyr, `Digital Filter and Square Timing Recovery’, IEEE Trans. Commun., Vol. 36, No. 5, pp. 605–612, May 1988.CrossRefGoogle Scholar
  47. [47]
    E. Panayirci, `Jitter Analysis of a Phase-Locked Digital Timing Recovery System’, IEE Proc.-I, Vol. 139, No. 3, pp. 267–275, June 1992.Google Scholar
  48. [48]
    A.E. Payzin, `Analysis of a Digital Bit Synchronizer’, IEEE Trans. Commun., Vol. 31, No. 4, pp. 554–560, Apr. 1983.zbMATHCrossRefGoogle Scholar
  49. [49]
    A. Pottbäcker, U. LLangmann, and H.-U. Schreiber, `A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s’, IEEE J. Solid-State Circuits, Vol. 27, No. 12, pp. 1747–1751, Dec. 1992.CrossRefGoogle Scholar
  50. [50]
    S.Ú.H. Qureshi, `Timing Recovery for Equalized Partial-Response Systems’, IEEE Trans. Commun., Vol. 24, pp. 1326–1331, Dec. 1976.CrossRefGoogle Scholar
  51. [51]
    R. Raheli, A. Pincin and R. Colombo, `On MMSE Timing Recovery Using Over-sampling’, Proc. 1990Int. Zürich Seminar on Digital Communications,March 5–8, 1990, ETH Zürich, Switzerland, pp. 474–494.Google Scholar
  52. [52]
    C.R. Rao, `Minimum Variance and the Estimation of Several Parameters’, Proc. Cambridge Phil. Soc., Vol. 43, p. 280, 1947.zbMATHCrossRefGoogle Scholar
  53. [53]
    W. Rosenkrantz, `Phase-Locked Loops with Limiter Phase Detectors in the Presence of Noise’, IEEE Trans. Commun., Vol. 30, No. 10, pp. 2297–2304, Oct. 1982.CrossRefGoogle Scholar
  54. [54]
    E. Roza, `Analysis of Phase-Locked Timing Extraction Circuits for Pulse-Code Transmission’, IEEE Trans. Commun., Vol. 22, pp. 1236–1249, Sept. 1974.CrossRefGoogle Scholar
  55. [55]
    B.R. Saltzberg, `Timing Recovery for Digital Synchronous Data Transmission’, Bell Syst. Tech. J., Vol. 46, pp. 593–622, March 1967.Google Scholar
  56. [56]
    H. Sari, L. Desperben and S. Mondi, `Minimum Mean-Square Error Timing Recovery Schemes for Digital Equalizers’, IEEE Trans. Commun., Vol. 34, No. 7, pp. 694–702, Jul. 1986.CrossRefGoogle Scholar
  57. [57]
    H. Sari, H. Houeix, and G. Karam, `Phase and Frequency Detectors for Clock Synchronization in High-Speed Optical Transmission Systems’, European Trans. on Telecommun. and Related Technologies, Vol. 5, No. 5, pp. 635–641, Sept./Oct. 1994.Google Scholar
  58. [58]
    M.K. Simon, `Optimization of the Performance of a Digital-Data-Transition Tracking Loop’, IEEE Trans. Commun. Technol., Vol. 18, pp. 686–689, Oct. 1970.CrossRefGoogle Scholar
  59. [59]
    E.F. Stikvoort and J.A.C. van Rens, `An All-Digital Bit Detector for Compact Disc Players’, IEEE J. Selected Areas Commun., Vol. 10, No. 1, pp. 191–200, Jan. 1992.CrossRefGoogle Scholar
  60. [60]
    T. Suzuki, H. Takatori, M. Ogawa and K. Tomooka, `Line Equalizer for a Digital Subscriber Loop Employing Switched Capacitor Technology’, IEEE Trans. Commun., Vol. 30, pp. 2074–2082, Sept. 1982.CrossRefGoogle Scholar
  61. [61]
    M. Tanaka and N. Watanabe, Bittaktsignal-Rückgewinnungsschaltung, German patent DE 31 16 054 C 2, issued Dec. 12, 1991.Google Scholar
  62. [62]
    R.C.E. Thomas, `Frequency Comparator Performs Double Duty’, EDN, pp. 29–33, Nov. 1, 1970.Google Scholar
  63. [63]
    Y.P. Tsividis and J.O. Voorman (Eds.), Integrated Continuous-Time Filters. New York: IEEE Press, 1993.Google Scholar
  64. [64]
    C.-P.J. Tzeng, D.A. Hodges and D.G. Messerschmitt, `Timing Recovery in Digital Subscriber Loops Using Baudrate Sampling’, IEEE J. Selected Areas Commun., Vol. 4, pp. 1302–1311, Nov. 1986.CrossRefGoogle Scholar
  65. [65]
    K.J. Wouda and W. Reijntjens, Arrangement for Generating a Clock Signal, European patent No. 0 162 505 (filed 18. 04. 85 ).Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1996

Authors and Affiliations

  • Jan W. M. Bergmans
    • 1
  1. 1.Philips ResearchEindhovenThe Netherlands

Personalised recommendations