• Donald E. Thomas
  • Philip R. Moorby


The exercises at the end of the previous Chapters have been short questions to help you think about the material in the Chapter. This Chapter contains two projects that each encompass many aspects of the Verilog language. Each of these projects has been used in Junior level university classes for electrical and computer engineering students.


Clock Signal Clock Period Direct Memory Access Clock Pulse NAND Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 1996

Authors and Affiliations

  • Donald E. Thomas
    • 1
  • Philip R. Moorby
    • 2
  1. 1.Carnegie Mellon UniversityUSA
  2. 2.Avid Technology, Inc.USA

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