Low Power Folding A/D Converters

  • Ardie G. W. Venes
  • Bram Nauta
  • Rudy J. van de Plassche

Abstract

This paper describes the design and implementation of low power folding A/D converters in CMOS technology. The main advantage of the folding architecture is a reduced number of comparators by the implementation of an analog preprocessing circuit, resulting in a very compact, low power and high speed A/D converter. Design issues and low power implementation of the analog preprocessing and comparators are discussed. Two prototype folding A/D converters are presented, one for 5 V supply voltage and one for 3.3 V supply voltage. The first design operates at 70 MHz clock frequency and dissipates 110 mW. The 3.3 V low voltage design operates at 45 MHz and dissipates only 45 mW. Chip area is 0.75 mm2 in 0.8 μm CMOS technology.

Keywords

Power Dissipation Differential Pair Versus Supply Voltage Meta Stable State Clock Jitter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer Science+Business Media Dordrecht 1996

Authors and Affiliations

  • Ardie G. W. Venes
    • 1
  • Bram Nauta
    • 1
  • Rudy J. van de Plassche
    • 1
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands

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