Low Power Folding A/D Converters

  • Ardie G. W. Venes
  • Bram Nauta
  • Rudy J. van de Plassche


This paper describes the design and implementation of low power folding A/D converters in CMOS technology. The main advantage of the folding architecture is a reduced number of comparators by the implementation of an analog preprocessing circuit, resulting in a very compact, low power and high speed A/D converter. Design issues and low power implementation of the analog preprocessing and comparators are discussed. Two prototype folding A/D converters are presented, one for 5 V supply voltage and one for 3.3 V supply voltage. The first design operates at 70 MHz clock frequency and dissipates 110 mW. The 3.3 V low voltage design operates at 45 MHz and dissipates only 45 mW. Chip area is 0.75 mm2 in 0.8 μm CMOS technology.


Power Dissipation Differential Pair Versus Supply Voltage Meta Stable State Clock Jitter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Nauta, B. and A. Venes, ‘A 70 MS/s 110 mW 8-b CMOS Folding and Interpolation A/D Converter’, ISSCC Digest of Technical Papers, 1995, p 276–277.Google Scholar
  2. [2]
    Plassche, R.J. van de, Integrated Analog-to-digital and Digital-to-Analog Converters’, Kluwer Academic Publishers, Boston/ Dordrecht/ London, 1994.CrossRefGoogle Scholar
  3. [3]
    Grift, R.E.J, van de et al., ‘An 8-bit Video ADC Incorporating Folding and Interpolation Techniques’, IEEE Journal of Solid-State Circuits, vol. 22, no. 6, Dec 1987.Google Scholar
  4. [4]
    Plassche, R.J. van de and P. Baltus, ‘An 8-bit 100 MHz Full Nyquist Analog-to-Digital Converter’, IEEE Journal of Solid-State Circuits, vol. 23, no. 6, Dec. 1988.Google Scholar
  5. [5]
    Valburg, J. van and R.J. van de Plassche, ‘An 8-b 650-MHz Folding ADC, IEEE Journal of Solid-State Circuits, vol. 27, no. 12, Dec. 1992.Google Scholar
  6. [6]
    Pelgrom, M.J.M. et al., ‘Matching properties of MOS Transistors’, IEEE Journal of Solid-State Circuits, vol. 24, no. 5, Oct. 1989.Google Scholar
  7. [7]
    Veendrick, H.J.M., ‘The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate’, IEEE Journal of Solid-State Circuits, vol. 15, no. 2, Apr. 1980.Google Scholar
  8. [8]
    Kattmann, K. and J. Barrow, ‘A technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters’, ISSCC Digest of Technical Papers, 1991, p.170.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1996

Authors and Affiliations

  • Ardie G. W. Venes
    • 1
  • Bram Nauta
    • 1
  • Rudy J. van de Plassche
    • 1
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands

Personalised recommendations