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Design of High-Speed Low-Power Sample-and-Hold Amplifiers for Low-Voltage Applications

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Analog Circuit Design
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Abstract

This paper describes design techniques for high-speed low-voltage sample-and-hold amplifiers used at the front-end of analog-to-digital converters. These techniques have been utilized in two 3-V sampling circuits, namely, a 100-MHz 10-mW all-npn implementation employing capacitive coupling between the input and output, and a 200-MHz 15-mW BiCMOS design using a low-voltage sampling switch. Each circuit allows swings of 1.5 V, providing 10 bits of dynamic range in a 3-V system.

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References

  1. B. Razavi, “A 100-MHz 10-mW All-NPN Sample-and-Hold Circuit with 3-V Supply,” Proceedings of European Solid-State Circuits Conf, pp. 192–195, Sept. 1994.

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  3. B. Razavi, Principles of Data Conversion System Design, IEEE Press, New York, 1995.

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  7. J. Sung et al, “BEST2 — A high performance super self-aligned 3V/5V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications,” Proc. IEEE CICC, pp. 15–18, May 1994.

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© 1996 Springer Science+Business Media Dordrecht

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Razavi, B. (1996). Design of High-Speed Low-Power Sample-and-Hold Amplifiers for Low-Voltage Applications. In: Huijsing, J.H., van de Plassche, R.J., Sansen, W.M.C. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2462-2_5

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  • DOI: https://doi.org/10.1007/978-1-4757-2462-2_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5157-1

  • Online ISBN: 978-1-4757-2462-2

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