Design of High-Speed Low-Power Sample-and-Hold Amplifiers for Low-Voltage Applications

  • Behzad Razavi


This paper describes design techniques for high-speed low-voltage sample-and-hold amplifiers used at the front-end of analog-to-digital converters. These techniques have been utilized in two 3-V sampling circuits, namely, a 100-MHz 10-mW all-npn implementation employing capacitive coupling between the input and output, and a 200-MHz 15-mW BiCMOS design using a low-voltage sampling switch. Each circuit allows swings of 1.5 V, providing 10 bits of dynamic range in a 3-V system.


Power Dissipation Analog Input Voltage Swing Junction Capacitance Gain Error 
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Copyright information

© Springer Science+Business Media Dordrecht 1996

Authors and Affiliations

  • Behzad Razavi
    • 1
  1. 1.AT&T Bell LaboratoriesHolmdelUSA

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