A 2 GHz Low-Power Frequency Synthesizer

  • Tom A. D. Riley
  • Miles A. Copeland


This paper describes techniques for achieving low power in a bipolar or BiCMOS synthesizer chip. The introductory material describes two types of fractional-N synthesizers and how these synthesizers could be used to reduce overall power consumption in a portable radio handset. The rest of the paper provides some tutorial review of bipolar logic design with some refinements for low power. The low power design is compared to previous versions in two different fabrication processes.


Charge Pump Tail Current Logic Block Switching Transistor Loop Bandwidth 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1996

Authors and Affiliations

  • Tom A. D. Riley
    • 1
  • Miles A. Copeland
    • 1
  1. 1.Carleton UniversityOttawaCanada

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