Computer-Aided testability analysis for analog circuits

  • Bert Atzema
  • Eric Bruls
  • Manoj Sachdev
  • Taco Zwemstra


Test development of analog circuits currently is a manual, time consuming, and experience based task. The specification driven approach does not allow for an objective quantification of the test effectiveness. This paper describes how the technique of Inductive Fault Analysis can be used to quantify the test effectiveness on basis of realistic data on manufacturing defects. Experiences with the tool suite developed to support this analysis show that realistic analog circuits often imply long fault simulation times. It is shown how high-level models are incorporated in the strategy to alleviate this problem. Some examples of applications to real circuits conclude this paper.


Analog Circuit Digital Circuit Tolerance Analysis Defect Coverage Fault Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1996

Authors and Affiliations

  • Bert Atzema
    • 1
  • Eric Bruls
    • 1
  • Manoj Sachdev
    • 1
  • Taco Zwemstra
    • 1
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands

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