Pre and Post-Synthesis Simulation

Abstract

Simulation is the process of verifying the functionality and timing of a design against its original specifications. In the ASIC design flow, designers perform functional simulation prior to synthesis. After synthesis, gate level simulation is performed on the netlist generated by synthesis. This chapter has been included to provide a better understanding of the synthesis-based ASIC design flow. Since the focus of this book is primarily synthesis, this chapter does not delve into details of either simulation or the simulation tool used. The simulator used is the Synopsys VHDL System Simulator (VSS). Simulation using Verilog is beyond the scope of this book.