Abstract
Verilog provides a set of 26 gate level primitives for modeling the actual logic implementation of a digital system. From these primitives, presented in Chapter 4, larger structural models may be hierarchically described. This chapter presents an advanced method for extending the set of gate level primitives to include user-defined combinational, and level- and edge-sensitive sequential circuits.
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© 1995 Springer Science+Business Media New York
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Thomas, D.E., Moorby, P.R. (1995). Defining Gate Level Primitives. In: The Verilog® Hardware Description Language. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2365-6_5
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DOI: https://doi.org/10.1007/978-1-4757-2365-6_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2367-0
Online ISBN: 978-1-4757-2365-6
eBook Packages: Springer Book Archive