A Fully integrated 1V/100μA high bitrate CP-FSK receiver
This paper presents a CMOS low power fully integrated FSK receiver to be used in small short distance remote control systems or in power line communication systems, where modest carrier frequencies are employed. Carrier frequency bias currents, receiver bandwidth, bit rate, data jitter and loop filter in the all digital symbol synchroniser are programmable. The chip is compatible with a recently developed Continuous Phase FSK transmitter, consumes typically 100μW and measures 18mm2. The low power consumption and high selectivity is obtained by direct conversion (zero IF) of the RF signals to base band. The problem of output data jitter at high bit rates is effectively solved by means of analog oversampling. DC offset problems have been circumvented by means of chopper amplifiers in the switched capacitor baseband filter/amplifier sections.
KeywordsAutomatic Gain Control Loop Filter Signal Pair Input Amplifier Voltage Multiplier
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