New RF Devices Based on High Precision CMOS Time-to-Digital and Digital-to-Time Converters

  • Juha Rapeli


The implementation of FM/PM demodulation based on direct cycle time measurement is feasible and attractive way to integrate FM receivers. Cycle time measurement is based on CMOS delay lines used as Time-to-Digital Converters (TDC). An experimental chip shows performance, size and current consumption comparable with the traditional quadrature phase shifter based IF/FM demodulator circuits and the level of achievable integration to be much better.

The use of CMOS delay lines as Digital-to-Time Converters (DTC) together with interpolation principle makes it possible control time intervals down to a few pico seconds. The interpolating phase locked loop frequency synthesizer, (IDPLL), is shown capable to adjust the phase of up to 2 GHz RF signals down to a small fraction of cycle time, thus facilitating small frequency steps, fast switching and settling together with low noise, and finally a digitally controllable, simple means for phase and frequency modulation.

With the current state-of-the art 63/64 tap CMOS delay lines with 40 ns range show an accuracy better than ± 0.5 ns which, in turn, results in an FM demodulator and an IDPLL synthesizer performance meeting radio telephony requirements.


Delay Line Loop Filter Frequency Synthesizer Delay Element Phase Comparator 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media Dordrecht 1994

Authors and Affiliations

  • Juha Rapeli
    • 1
  1. 1.Nokia Mobile Phones LtdOuluFinland

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