High Speed Folding ADC’s

  • Johan van Valburg
  • Rudy J. van de Plassche


This paper describes the evolution steps used within the Philips company on the development of a high speed analog to digital converter (ADC) with a low power consumption and a small die size. Analog preprocessing of the input signal before conversion to binary information is a key function in all the explained systems.


Reference Voltage Delay Variation Code Transition Decision Stage Differential Pair 
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  1. [1]
    R.J. v.d. Plassche, P. Baltus, “An 8 bit 100 MHz Full Nyquist ADC”, IEEE Journal of Solid State Circuits, Vol. 23, No. 6, December 1988, pp. 1334–1344.CrossRefGoogle Scholar
  2. [2]
    R. v.d. Grift et al., “An 8 bit video ADC incorporating folding and interpolation techniques”, IEEE Journal of Solid State Circuits, Vol. 22, No. 6, December 1987, pp. 944–953.CrossRefGoogle Scholar
  3. [3]
    R.J. v.d. Plassche, “High speed and high resolution analog to digital and digital to analog converters”, Ph.D. Thesis, Delft University of Technology, Delft, The Netherlands, 1989.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1993

Authors and Affiliations

  • Johan van Valburg
    • 1
  • Rudy J. van de Plassche
    • 1
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands

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