High Speed Sample and Hold and Analog-to-Digital Converter Circuits

  • John Corcoran

Abstract

Architectures for analog-to-digital (A/D) conversion above 100 Msamples-per-second are described. The well known pipeline and flash configurations are examined, including variations which reduce complexity and power consumption. Static and dynamic errors common to flash architecture A/D circuits are enumerated. The advantages of sample and hold (S/H) circuits in reducing dynamic errors in flash converters are described. A simple model for sample and hold circuits is used to predict S/H performance limits and sources of error.

Keywords

Input Signal Dynamic Error Slew Rate Gray Code Pipeline Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Yukio Akazawa, et al., “A 400 MSPS 8b Flash AD Conversion LSI”, ISSCC Digest of Technical Papers, 1987, pp. 98–99Google Scholar
  2. [2]
    Bruce Peetz, et al., “An 8-bit 250 Megasample per Second Analog-to-Digital Converter: Operation Without a Sample and Hold”, IEEE Journal of Solid-State Circuits, vol. SC-21, no. 6, December 1986, pp. 997–1002CrossRefGoogle Scholar
  3. [3]
    Yuji Gendai, et al., “An 8b 500MHz ADC”, ISSCC Digest of Technical Papers, 1991, pp. 172–173Google Scholar
  4. [4]
    Ken Poulton, Hewlett-Packard Laboratories, private communicationGoogle Scholar
  5. [5]
    Robert A. Blauschild, “An 8b 5Ons Monolithic A/D Converter with Internal S/H”, ISSCC Digest of Technical Papers, 1983, pp. 178–179Google Scholar
  6. [6]
    Robert Jewett, et al., “A 12b 20MS/s Ripple-through ADC”, ISSCC Digest of Technical Papers, 1992, pp. 34–35Google Scholar
  7. [7]
    Stephen H. Lewis, et al., “A Pipelined 5 MHz 9b ADC”, ISSCC Digest of Technical Papers, 1987, pp. 210–211Google Scholar
  8. [8]
    David Robertson, et al., “A Wideband 10-bit, 20 MSPS Pipelined ADC using Current-Mode Signals”, ISSCC Digest of Technical Papers, 1990, pp. 160–161Google Scholar
  9. [9]
    John J. Corcoran, et al., “A 400MHz 6b ADC”, ISSCC Digest of Technical Papers, 1984, pp. 294–295Google Scholar
  10. [10]
    T.W. Henry, et al., “Direct Flash Analog-to-Digital Converter and Method”, U.S. Patent 4, 386, 339Google Scholar
  11. [11]
    Adrian P. Brokaw, “Parallel Analog-to-Digital Converter”, U.S. Patent 4, 270, 118Google Scholar
  12. [12]
    Rob E.J. van de Grift, et al., “An 8b 50 MHz Video ADC with Folding and Interpolation Techniques”, ISSCC Digest of Technical Papers, 1987, pp. 94–95Google Scholar
  13. [13]
    Rudy van de Plassche, et al., “An 8b 100 MHz Folding ADC”, ISSCC Digest of Technical Papers, 1987, pp. 94–95Google Scholar
  14. [14]
    Johan van Valburg, et al., “An 8b 650 MHz Folding ADC”, ISSCC Digest of Technical Papers, 1992, pp. 30–31Google Scholar
  15. [15]
    Yoji Yoshii, et al., “An 8b 350 MHz Flash ADC”, ISSCC Digest of Technical Papers, 1987, pp. 96–97Google Scholar
  16. [16]
    V.E. Garuts, et al., “A Dual 4-bit, 1.5 Gs/s Analog-to-Digital Converter”, 1988 Bipolar Circuits and Technology Meeting Proceedings, pp.141–144Google Scholar
  17. [17]
    Ken Rush, et al., “A 4 GHz 8b Data Acquisition System”, ISSCC Digest of Technical Papers, 1991, pp. 176–177Google Scholar
  18. [18]
    Ken Poulton, et al., “A 1-GHz 6-bit ADC System”, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, December 1987Google Scholar
  19. [19]
    S. Prasad, et al., “An Implant-Free 45 GHz A1GaAs/GaAs HBT IC Technology Incorporating 1.4 THz Schottky Diodes”, 1991 Bipolar Circuits and Technology Meeting Proceedings, pp.79–82Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1993

Authors and Affiliations

  • John Corcoran
    • 1
  1. 1.Hewlett-Packard LaboratoriesPalo AltoUSA

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