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A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits

  • Enrico Malavasi
  • Henry Chang
  • Alberto Sangiovanni-Vincentelli
  • Edoardo Charbon
  • Umakanta Choudhury
  • Eric Felt
  • Gani Jusuf
  • Edward Liu
  • Robert Neff

Abstract

This paper describes a top-down, constraint-driven design methodology for analog integrated circuits. Some of the tools that support this methodology are described. These include behavioral simulation tools, tools for physical assembly, and module generators. Finally, examples of behavioral simulation with optimization and physical assembly are provided to better illustrate the methodology and its integration with the tool set.

Keywords

Analog Circuit Solid State Circuit Analog Block Behavioral Simulation Analog Integrate Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    J. Rijmenants et al., “ILAC: An Automated Layout Tool for Analog CMOS Circuits”, IEEE Journal of Solid State Circuits, Vol. 24, no. 2, pp. 417–425, April 1989.CrossRefGoogle Scholar
  2. [2]
    M. Degrauwe et al., “IDAC: An Interactive Design Tool for Analog CMOS Circuits”, IEEE Journal of Solid State Circuits, Vol.SC-22, No. 6, pp. 1106–1116, December 1987.Google Scholar
  3. [3]
    J.M. Cohn, D.J. Garrod, R.A. Rutenbar and L.R. Carley, “KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing”, IEEE Journal of Solid State Circuits, Vol. 26, no. 3, pp. 330–342, March 1991.CrossRefGoogle Scholar
  4. [4]
    S.W. Mehranfar, “A Technology-Independent Approach to Custom Analog Cell Generation”, IEEE Journal of Solid State Circuits, Vol. 26, n. 3, pp. 386–393, March 1991.CrossRefGoogle Scholar
  5. [5]
    E. Liu, A. Sangiovanni-Vincentelli, G. Gielen and P. Gray, “A Behavioral Representation for Nyquist Rate A/D Converters”, in Proc. IEEE ICCAD, pp. 386–389, November 1991.Google Scholar
  6. [6]
    Mark Sitkowski, “The Macro Modeling of Phase Locked Loops for the Spice Simulator”, IEEE Circuits and Devices Magazine, Vol. 7, No. 2, pp. 11–15; March 1991.CrossRefGoogle Scholar
  7. [7]
    U. Choudhury and A. Sangiovanni-Vincentelli, “Constraint Generation for Routing Analog Circuits”, in Proc. Design Automation Conference, pp. 561–566, June 1990.Google Scholar
  8. [8]
    S. Kirkpatrick, C. Gelatt and M. Vecchi, “Optimization by simulated annealing”, Science, Vol. 220, n. 4598, pp. 671–680, May 1983.zbMATHCrossRefMathSciNetGoogle Scholar
  9. [9]
    E. Charbon, E. Malavasi, U. Choudhury, A. Casotto and A. Sangiovanni-Vincentelli, “A Constraint-Driven Placement Methodology for Analog Integrated Circuits”, in Proc. IEEE Custom Integrated Circuits Conference, May 1992.Google Scholar
  10. [10]
    E. Malavasi, E. Charbon, G. Jusuf, R. Totaro and A. SangiovanniVincentelli, “Virtual Symmetry Axes for the Layout of Analog IC’s”, in Proc. 2 nd ICVC, Seoul, Korea, pp. 195–198, October 1991.Google Scholar
  11. [11]
    U. Choudhury and A. Sangiovanni-Vincentelli, “An Analytical-Model Generator for Interconnect Capacitances”, in Proc. IEEE Custom Integrated Circuits Conference, pp. 861–864, May 1991.Google Scholar
  12. [12]
    U. Choudhury and A. Sangiovanni-Vincentelli, “Constraint-Based Channel Routing for Analog and Mixed-Analog Digital Circuits”, in Proc. IEEE ICCAD, pp. 198–201, November 1990.Google Scholar
  13. [13]
    H.H. Chen and E.S. Kuh, “A Gridless Variable-Width Channel Router”, IEEE Trans. on CAD, Vol.CAD-5, n. 4, October 1986.Google Scholar
  14. [14]
    E. Malavasi, U. Choudhury and A. Sangiovanni-Vincentelli, “A Routing Methodology for Analog Integrated Circuits”, in Proc. IEEE ICCAD, pp. 202–205, November 1990.Google Scholar
  15. [15]
    G.W. Clow, “A Global Routing Algorithm for General Cells”, in Proc. Design Automation Conference, pp. 45–51, 1984.CrossRefGoogle Scholar
  16. [16]
    C. Lee, “An algorithm for path connections and applications”, IRE Trans. Electron. Computer, Vol.EC-10, pp. 346–365, Sep 1961.Google Scholar
  17. [17]
    E. Felt, E. Charbon, E. Malavasi and A. Sangiovanni-Vincentelli, “An Efficient Methodology for Symbolic Compaction of Analog IC’s with Multiple Symmetry Constraints”, in subm. to the European Design Automation Conference, 1992.Google Scholar
  18. [18]
    A.R. Newton, “Symbolic Layout and Procedural Design”, in Design Systems for VLSI Circuits, pp.65–112. De Micheli et al. Eds., Martinus Nijhoff, 1987.Google Scholar
  19. [19]
    J.R. Burns and A.R. Newton, “SPARCS: A New Constraint-Based IC Symbolic Layout Spacer”, in Proc. IEEE Custom Integrated Circuits Conference, pp. 534–539, 1986.Google Scholar
  20. [20]
    J.L. Burns, “Techniques for IC Symbolic Layout and Compaction”, Memorandum UCB/ERL M90/103, UCB, November 1990.Google Scholar
  21. [21]
    R. Harjani et al., “A Prototype Framework for Knowledge-Based Analog Circuit Synthesis”, in Proc. Design Automation Conference, pp. 42–49, 1987.Google Scholar
  22. [22]
    H.Y. Koh, C.H. Séquin and P.R. Gray, “Automatic synthesis of operational amplifiers based on analytic circuit models”, in Proc. IEEE ICCAD, pp. 502–505, 1987.Google Scholar
  23. [23]
    M.G. DeGrauwe et al., “An Analog Expert Design of Analog Integrated Circuits”, in Proc. IEEE International Solid-State Circuits Conference, pp. 212–213, 1987.Google Scholar
  24. [24]
    G. Jusuf, P.R. Gray and A. Sangiovanni-Vincentelli, “CADICS–Cyclic Analog-To-Digital Converter Synthesis”, in Proc. IEEE ICCAD, pp. 286–289, November 1990.Google Scholar
  25. [25]
    H. Yaghutiel, A. Sangiovanni-Vincentelli and P.R. Gray, “A Methodology for Automated Layout of Switched-Capacitor Filters”, in Proc. IEEE ICCAD, pp. 444–447, 1986.Google Scholar
  26. [26]
    H.Y. Koh, C.H. Séquin and P.R. Gray, “Automatic Layout Generation for CMOS Operational Amplifiers”, in Proc. IEEE ICCAD, pp. 548–551, November 1988.Google Scholar
  27. [27]
    G. Szentirmai, “FILSYN - A General Purpose Filter Synthesis Program”, in Proc. of the IEEE, pp.65:1443–1458, October 1977.Google Scholar
  28. [28]
    D. Lucas, “Analog Silicon Compiler For Switched Capacitor Filters”, in Proc. IEEE ICCAD, pp. 506–513, November 1987.Google Scholar
  29. [29]
    M.G. DeGrauwe et al., “A Micropower CMOS Instrumentation Amplifier”, in IEEE Journal of Solid State Circuits, June 1985.Google Scholar
  30. [30]
    H. Ohara et al., “A CMOS Programmable Self-Calibrating 13-bit 8-channel Data Acquisition Peripheral”, IEEE Journal of Solid State Circuits, pp. 362–369, December 1987.Google Scholar
  31. [31]
    P.E. Allen and P.R. Barton, “A Silicon Compiler for Successive Approximation A/D and D/A Converters”, in Proc. IEEE Custom Integrated Circuits Conference, pp. 552–555, 1986.Google Scholar
  32. [32]
    M.W. Hauser et al., “MOS ADC-Filter Combination That Does Not Require Precision Analog Components”, in Proc. IEEE International Solid-State Circuits Conference, February 1985.Google Scholar
  33. [33]
    B.H. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation Analog-To-Digital Converters”, IEEE Journal of Solid State Circuits, pp. 1298–1308, December 1988.Google Scholar
  34. [34]
    G. Jusuf and P.R. Gray, “An Improved 1-Bit/Cycle Algorithmic A/D Converter”, Memorandum UCB/ERL M90/69, University of California at Berkeley, August 1990.Google Scholar
  35. [35]
    S.H. Lewis, “Video-Rate Analog-To-Digital Conversion Using Pipelined Architectures”, Ph.d. thesis, University of California at Berkeley, November 1987.Google Scholar
  36. [36]
    W. Nye, D.C. Riley, A. Sangiovanni-Vincentelli and A.L. Tits, “DELIGHT-SPICE: An Optimization-Based System for the Design of Integrated Circuits”, IEEE Trans. on CAD, Vol. 7, n. 4, pp. 501–519, April 1988.Google Scholar
  37. [37]
    R.W. Brodersen et al., Users’ Manual, Dept. of EECS, University of California at Berkeley, 1990.Google Scholar
  38. [38]
    G. Jusuf, P.R. Gray and A. Sangiovanni-Vincentelli, “A Compiler for CMOS Analog-To-Digital Converters”, in TECHCON, pp. 347–350, October 1990.Google Scholar
  39. [39]
    L. Stockmeyer, “Optimal Orientation of Cells in Slicing Floorplan Designs”, Information and Control, Vol. 57, No. 2/3, pp. 91–101, May 1983.zbMATHCrossRefMathSciNetGoogle Scholar
  40. [40]
    J. Burns, A. Casotto, M. Igusa, F. Marron, F. Romeo, A. Sangiovanni-Vincentelli, C. Sechen, H. Shin, G. Srinath and H. Yaghutiel, “Mosaico: An integrated Macro-cell Layout System”, in VLSI ‘87, Vancouver, Canada, Aug 1987.Google Scholar
  41. [41]
    H. Chang, A. Sangiovanni-Vincentelli, F. Balarin, E. Charbon, U. Choudhury, G. Jusuf, E. Liu, E. Malavasi, R. Neff and P. Gray, “A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits”, in Proc. IEEE Custom Integrated Circuits Conference, May 1992.Google Scholar
  42. [42]
    L.R. Carley et al., “ACACIA: The CMU Analog Design System”, in Proc. IEEE Custom Integrated Circuits Conference, 1989.Google Scholar
  43. [43]
    J.M. Shyu and A. Sangiovanni-Vincentelli, “ECSTASY: A new Environment for IC Design Optimization”, in Proc. IEEE ICCAD, pp. 484–487, November 1988.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1993

Authors and Affiliations

  • Enrico Malavasi
    • 1
  • Henry Chang
    • 1
  • Alberto Sangiovanni-Vincentelli
    • 1
  • Edoardo Charbon
    • 1
  • Umakanta Choudhury
    • 1
  • Eric Felt
    • 1
  • Gani Jusuf
    • 1
  • Edward Liu
    • 1
  • Robert Neff
    • 1
  1. 1.Department of Electrical Engineering and Computer SciencesUniversity of CaliforniaBerkeleyUSA

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