Structure generation

Abstract

The target architecture of CATHEDRAL-II is a dedicated interconnection of parameterised execution units (figure 2.5). The structure of a CATHEDRAL-II chip therefore consists of

• the netlist of the bit-level interconnections between the data path execution units and the controller execution unit. This includes data buses, test buses, scan paths, flags and instruction bits. The interconnection network also implements all type casts in hardware, and assures that signals are aligned correctly in registers, on buses and on operators.

• the execution unit parameters. The internal structure of all execution units, including the controller, memories and data paths, is fixed. Execution unit instances are generated by instantiating the parameters of structural templates, e.g., by the controller generator CGE [Zeg90] or the data path module generator MGE [Six86].