Implementation of data structures

  • Jan Vanhoof
  • Karl Van Rompaey
  • Ivo Bolsens
  • Gert Goossens
  • Hugo De Man
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 216)

Abstract

Next to operations on scalar signals, state-of-the-art DSP algorithms for complex, medium-throughput applications include operations on multidimensional data structures. Efficient storage methods and address generation techniques are therefore crucial in DSP ASIC design. In this chapter, we will identify and formalise a strategy and some important optimisation tasks for compiling multidimensional data structures into dual-port register files and single-port SRAMs. Memory management refers to all activities concerning the organisation of mem ory in an ASIC. This includes
  • the selection of a memory type and instance for each data structure. A delay line for instance, can be stored in RAM or in a register file.

  • the organisation of data structures per memory device, e.g., two matrices can share the same RAM locations if they are not alive simultaneously.

  • the internal organisation of each data structure in a particular part of the memory, e.g., a matrix may be stored row-by-row or column-by-column.

  • the address generation. For instance, addresses may be computed at runtime or stored in a ROM table.

Keywords

Delay Line Storage Location Register File Control Step Physical Address 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1993

Authors and Affiliations

  • Jan Vanhoof
    • 1
  • Karl Van Rompaey
    • 1
  • Ivo Bolsens
    • 1
  • Gert Goossens
    • 1
  • Hugo De Man
    • 1
  1. 1.IMEC vzwUSA

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