Via Minimization and Over-the-Cell Routing

  • Naveed A. Sherwani

Abstract

After a chip is completely routed, the layout is functionally complete and can be sent for fabrication. However, the layout is usually improved to reduce the possibility of fabrication errors, reduce the total chip area and therefore, improve performance. In this chapter, we will discuss two methods of improving detailed routing: via minimization and over-the-cell routing.

Keywords

Channel Height Cluster Graph Channel Density Circle Graph Permutation Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1993

Authors and Affiliations

  • Naveed A. Sherwani
    • 1
  1. 1.Western Michigan UniversityUSA

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