Abstract
After a chip is completely routed, the layout is functionally complete and can be sent for fabrication. However, the layout is usually improved to reduce the possibility of fabrication errors, reduce the total chip area and therefore, improve performance. In this chapter, we will discuss two methods of improving detailed routing: via minimization and over-the-cell routing.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1993 Springer Science+Business Media New York
About this chapter
Cite this chapter
Sherwani, N.A. (1993). Via Minimization and Over-the-Cell Routing. In: Algorithms for VLSI Physical Design Automation. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2219-2_8
Download citation
DOI: https://doi.org/10.1007/978-1-4757-2219-2_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2221-5
Online ISBN: 978-1-4757-2219-2
eBook Packages: Springer Book Archive