Physical Design Automation of FPGAs

  • Naveed A. Sherwani


Despite advances in VLSI design automation, the time—to—market for a chip is unacceptable for many applications. The key problem is time taken due to fabrication of chips, and therefore there is a need to find new technologies, which minimize the fabrication time. Gate Arrays use less time in fabrication as compared to full—custom chips, since only routing layers are fabricated on top of pre—fabricated wafer. However, fabrication time for gate—arrays is still unacceptable for several applications. In order to reduce time to fabricate interconnects, programmable devices have been introduced, which allow users to program the devices as well as the interconnect. In this way all custom fabrication steps are eliminated.


Directed Acyclic Graph Field Programmable Gate Array Segmented Model Physical Design Logic Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media New York 1993

Authors and Affiliations

  • Naveed A. Sherwani
    • 1
  1. 1.Western Michigan UniversityUSA

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