Abstract
Design for Testability (DFT) is a subject covering a huge amount material. The 1983 survey by Williams and Parker [Will83] is still remarkably current in its enumeration of DFT techniques (it lacks Boundary-Scan of course), but many of the contexts have changed. For example, signature analysis testing is now conducted on-chip, though it started as a board-level technique. This reflects the incredible increase in the density of Integrated Circuit (IC) components. In 1983, the 1149.1 Standard would have been largely impractical because the logic needed to implement it would have been a large fraction of an IC. Today, we are seeing ICs designed with significant amounts of on-chip testing circuitry, including 1149.1. Without DFT, a VLSI component might not be economical to produce in volume.
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Of course within large, vertically integrated companies there may be vast quantities of software support for a particular DFT methodology. It will be interesting to see how the advent of testing Standards such as 1149.1 will influence this software.
The main cause of board shorts is the bridging of solder between adjacent pins, particularly with fine-pitch spacings.
This analysis should also take into account any exceptional currents that exist if shorted pin drivers conflict with each other or are tied to a supply voltage.
This test can be implemented using the 1149.1 INTEST function that both of these ICs support. The test in this case needs to differentiate a latch (’8373) from a flip-flop (’8374).
Note that the abuse studied was In-Circuit overdrive abuse, which is likely to be more stressful than driver conflicts, since an In-Circuit tester driver is usually far stronger than an IC driver. Do note that drivers shorted to Power or Ground suffer worst-case current flows and durations.
However, in certain applications where the cost of failure due to reduced component lifetime is extreme, this may be quite acceptable. Consider electronic health care products or airborne navigation systems as examples.
Be extremely wary to include the time to set up the tester, any reload times, and the time it requires to determine if a conflict exists. The time cannot be reliably predicted by simply multiplying the TCK cycle time by the number of TCK cycles in the longest expected test.
The actual BSDL CELL_INFO triple for this is, for example, (Output2, EXTEST, PI). “PI” is the parallel input that, for an output cell, must be the System Logic.
This description would be part of a user-defined VHDL package for cell design description as described in Chapter 2. The package would be referenced in the entity description for the IC in a “use” statement. The “SMOC” name would appear in the attribute BOUNDARY REGISTER.
The reversible cell in need of improvement is shown in figure 10–22 of the original 1149.1–1990 Standard. In BSDL, it is cell BC_6.
Bs If the control cell has been merged with an input cell, then it must capture the input pin state in that case.
If an IC has yet to be fabricated, then consider simulating the test patterns against a model of the IC, which is acceptable if the model and the resulting IC are good matches.
The verification of mapping is done to ensure the cell information in the BSDL attribute BOUNDARY_REGISTERis correct, which can be done using the EXTEST instruction.
Third, we have dynamically reconfigurable chains. These structures are essentially a set of simple chains that have their TDI/TDO data paths
The 1149.1 Working Group has not issued an opinion on the merits of dynamic reconfiguration. This capability seems to be more properly the realm of system-level test bus schemes, such as P1149.5.
The buffering IC cannot itself be an 1149.1 design (in the same chain) since its Boundary Register could prevent the TCK/TMS signals from being distributed.
See also the discussion of Boundary-Scan Masters in section 5.2.7.
To manage the two separate chains, nodal access to the TDI/TDO node at the junction of the two chains will be necessary. It will not be possible to run the two chains simultaneously; driving the second chain’s TDI overwrites TDO from the first.
The author knows of no ICs containing 1149.1 that perform logic-level conversion, at the time of this writing.
Remember that these constraints will not be honored by failures either.
They are the Texas Instruments 74ACT8990 and the ATT 479AA. Others may soon appear.
The vendors of Boundary-Scan masters usually supply supporting software for their components to facilitate prototyping and the development of microprocessor software or firmware. Such software is usually not of general use outside of this environment.
The selected register is a function of the instruction loaded into the TAP Instruction Register of the Linker/Selector IC.
The distinction between 1149.1 and P1149.5 becomes somewhat obscured by the existence of Boundary-Scan masters, linkers and selectors. This should point out that as of now, the system-level use of Boundary-Scan is not truly a settled matter; it is subject to much further study, experiment, trial and error.
This scan-based architecture predates the 1149.1 Standard and is significantly different in the details. The architecture is a precursor to the P1149.2 effort today.
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© 1992 Springer Science+Business Media New York
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Parker, K.P. (1992). Design for Boundary-Scan Testing. In: The Boundary-Scan Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2142-3_5
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DOI: https://doi.org/10.1007/978-1-4757-2142-3_5
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