Boundary-Scan Testing

  • Kenneth P. Parker


Boundary-Scan testing is aimed primarily at digital logic structures, although Boundary-Scan assets can provide invaluable resources for assisting with mixed digital/analog testing as well. This chapter covers various test approaches utilizing 1149.1.


Boundary Register Stimulus Pattern Counting Sequence Instruction Register Simple Chain 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 41.
    Application software must keep track of N by knowing what register is targeted by the current TAP instruction. A BSDL description contains the length of all registers and their associations with TAP instructions.Google Scholar
  2. 42.
    In practice, we would have preloaded the Boundary Register with the first set of data to be written by using a capture-shift-update cycle with SAMPLE/PRELOAD in effect. This data would then actually be written to the board-level nodes when passing through UPDATE-IR after loading the EXTEST instruction.Google Scholar
  3. 43.
    A typical “safe” pattern would use the data from the BSDL description safe subfield within the attribute BOUNDARY_ REGISTER description. This can be augmented with data needed to create safe board-level conditions as well.Google Scholar
  4. 44.
    The meaning of “Application Specific” has a very narrow definition in the industry. For the purpose of this discussion on the difficulty of testing, an ASIC could mean any one-of-a-kind design, including Programmable Gate Arrays (PGAs), Programmable Logic Devices (PLDs) and the like.Google Scholar
  5. 45.
    Structural problems in the electronics industry also contribute to the difficulty; tools for IC level testing of ASICs do exist, but are of little use at board test due to board-level constraints (nodal wiring) and to the difference in failure mechanisms of interest between the two contexts. Finally, the ASIC designer might have no motivation to solve board-level test problems.Google Scholar
  6. 46.
    Unpowered shorts testing“ is accomplished before power is applied to the board. It uses a series of very low voltage analog measurements that can isolate shorts between nailed nodes. Note that the power supply nodes would be included in this test, finding Power/Ground shorts as well as (nailed) signal nodes shorted to power nodes.Google Scholar
  7. 47.
    It is possible to use a “fault dictionary” approach to diagnose opens on inputs, if there is only one open, because this looks like a single stuck-at failure and matches the assumptions used to create dictionaries. If multiple failures exist, then the dictionary approach will usually give no diagnosis, or a false diagnosis.Google Scholar
  8. 48.
    Again as noted in Chapter 1, if output cells are designed following rule 10.6.1c(ii) of the Standard, then these outputs will be disabled for the duration of INTEST.Google Scholar
  9. 49.
    This is straightforward in those cases where System Logic input cells are disjoint from IC output cells. However, for bidirectional pins serviced by reversible Boundary Register cells, care must be taken to note when the cell is acting as an input versus an output.Google Scholar
  10. 50.
    The original BSDL paper [Park90b] attempts to describe the usage of instructions such as INTEST, RUNBIST and user-defined instructions. Subsequent study of this question for Supplement B of 1149.1 has shown such description to be quite difficult, similar to describing general waveforms (for which other efforts are already nearing completion, such as VHDL Waves). At this writing, there is no way to convey usage information within BSDL.Google Scholar
  11. 51.
    The same clocking complications noted in section 3.1.4 concerning just what is a “clock” apply here as well.Google Scholar
  12. 52.
    Again, assume that no operation of an optional TRST* signal occurs that would drive some chain members to TEST-LOGIC-RESET independently.Google Scholar
  13. 53.
    We assume that all ICs have been thoroughly tested before placement on a board. Damage from handling and placement, either physical (bent pins for example) or electrical (from Electrostatic Discharge—ESD for example) are our main concerns.Google Scholar
  14. 54.
    Alert readers may wonder why we would program these instructions when the TEST-LOGIC-RESET state sets these intrinsically; you could proceed directly to SHIFT-DR to read out the IDCODEs. The reason is many ICs do not contain IDCODE and place a single-bit Bypass Register with a captured “0” between TDI and TDO. This single bit cannot cause a transition on TDO so that we suffer even more ambiguity in isolating chain problems.Google Scholar
  15. 55.
    We are taking advantage of the fact that the vast majority of shorts are caused by improper connections (for example, bad solder) between physically adjacent I/O pins. Board shorts between printed node traces are usually eliminated before expensive components are loaded onto a board.Google Scholar
  16. 57.
    The process of applying power is more complex and time consuming than many realize. It might take several hundred milliseconds to stabilize a power voltage to specification. There may be several voltages to be applied in sequence. It also might take hundreds of milliseconds to turn power off!Google Scholar
  17. 58.
    Consider a short between three drivers of varying strengths, none overwhelming. Then consider the eight combinations of data they may have during the test. Next consider that each receiver of the combined nodes will interpret voltages as one or zero differently, particularly if there is any hysteresis at work. This example, entirely common, should give you concern about “simplifying” assumptions.Google Scholar
  18. 60.
    All receivers, including those within bidirectional structures that are not driving, should be checked to ensure the correct driver data is received from the node.Google Scholar
  19. 61.
    Supplement A (P1149. lA) to the Standard makes it a firm rule that drivers that are controlled by the same control cell must respond identically to the value loaded into that cell. The original standard allowed them to be different, causing obvious problems for test algorithms.Google Scholar
  20. 62.
    This could be a large number of expensive resources if many board locations exist where interactions are likely. This introduces a resource management problem (for example, by multiplexing) so that tester costs are not driven too high.Google Scholar
  21. 63.
    This parallel operation might not be possible if the allowable variations in how the ICs are clocked are not mutually compatible.Google Scholar

Copyright information

© Springer Science+Business Media New York 1992

Authors and Affiliations

  • Kenneth P. Parker
    • 1
  1. 1.Hewlett — Packard CompanyUSA

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