SOI CMOS Technology

  • Jean-Pierre Colinge
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 132)

Abstract

Complementary MOS (CMOS) is, by far, the technology of choice for the realization of integrated circuits on SOI substrates. This Chapter will compare CMOS processing on bulk silicon and on SOI wafers. Processing of both thin and thicker SOI films will be discussed. We will assume that circuit processing is carried out on commercially available substrates, such as SIMOX wafers. It is worthwhile keeping in mind that, unlike in the case of SOS, SOI wafers contain only silicon and silicon dioxide, and that the appearance of SOI wafers is very similar to that of bulk silicon wafers. As a consequence, SOI circuit processing can be carried out in standard bulk silicon processing lines. Mixed batches (containing both bulk and SOI substrates) can be processed as well.

Keywords

Threshold Voltage Body Contact Doping Profile Subthreshold Slope CMOS Inverter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Bibliography

  1. 4.1.
    T. Elewa, B. Kleveland, B. Boukriss, T. Ouisse, A. Chovet, S. Cristoloveanu, and J. Davis, Proceedings IEEE SOS/SOI Technology Conference, p. 35, 1989Google Scholar
  2. 4.2.
    R.K. Smeltzer and J.T. McGinn, Proceedings IEEE SOS/SOI Technology Workshop, p. 32, 1987Google Scholar
  3. 4.3.
    S.S. Tsao, D.M. Fletwood, V. Kaushik, A.K. Datye, L. Pfeiffer, and G.K. Celler, Proceedings IEEE SOS/SOI Technology Workshop, p. 33, 1987Google Scholar
  4. 4.4.
    R.B. Marcus and T.T. Sheng, J. Electrochem. Soc., Vol. 129, p. 1278, 1982CrossRefGoogle Scholar
  5. 4.5.
    M. Matloubian, R. Sundaresan, and H. Lu, Proceedings IEEE SOS/SOI Technology Workshop, p. 80, 1988Google Scholar
  6. 4.6.
    M. Haond and O. Le Néel, Proceedings IEEE SOS/SOI Technology Conference, p. 132, 1990, and O. Le Néel, M.D. Bruni, J. Galvier, and M. Haond, in “ESSDERC 90”, Adam Hilger Publisher, Ed. by. W. Eccleston and P.J. Rosser, p. 13, 1990Google Scholar
  7. 4.7.
    M. Haond, O. Le Neel, G. Mascarin, and J.P. Gonchond, Proceedings IEEE SOS/SOI Technology Conference, p. 68, 1989, and M. Haond, O. Le Neel, G. Mascarin, and J.P. Gonchond, in ESSDERC’89, European Solid-State Device Research Conference, Berlin, Ed. by. A. Heuberger, H. Ryssel and P. Lang, Springer-Verlag, p. 893, 1989Google Scholar
  8. 4.8.
    T. Aoki, M. Tomizawa, and A. Yoshii, IEEE Trans. on Electron Devices, Vol. 36, p. 1725, 1989CrossRefGoogle Scholar
  9. 4.9.
    J.P. Colinge, Proceedings IEEE SOS/SOI Technology Conference, p. 13, 1989Google Scholar
  10. 4.10.
    T. Nishimura, Y. Yamaguchi, H. Miyatake, and Y. Akasaka, Proceedings IEEE SOS/SOI Technology Conference, p. 132, 1989Google Scholar
  11. 4.11.
    N.K. Annamalai and M.C. Biwer, IEEE Trans. Nuclear Science, Vol. 35, p. 1372, 1988CrossRefGoogle Scholar
  12. 4.12.
    Y. Omura and K. Izumi, IEEE Trans. on Electron Devices, Vol. 35, p. 1391, 1988CrossRefGoogle Scholar
  13. 4.13.
    M. Haond, in ESSDERC’89, European Solid-State Device Research Conference, Berlin, Ed. by. A. Heuberger, H. Ryssel and P. Lang, Springer-Verlag, p. 881, 1989Google Scholar

Copyright information

© Springer Science+Business Media New York 1991

Authors and Affiliations

  • Jean-Pierre Colinge
    • 1
  1. 1.IMECBelgium

Personalised recommendations