Relative Control Generation
This chapter presents the synthesis of synchronous control logic to activate the functional units in the data-path according to a given schedule. Control synthesis is important because it affects the control flow of operations and hence directly impacts the overall performance of the resulting hardware. There are many different styles of control implementation, ranging from ROM-based microprogrammed controllers [SLP88] to finite-state machines [CR89] to distributed control [BCM+ 88]. In the simple case where the hardware model either does not contain any data-dependent delay operations or does not support multiple threads of concurrent execution flow, the control logic can be implemented using a microprogrammed controller or a single finite-state machine in a straightforward way.
KeywordsAdaptive Control Input Sequence Control Element Relative Control Constraint Graph
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