Sequencing Graph and Resource Model
This chapter presents the graph-based model of hardware behavior that is used as the underlying representation for the synthesis algorithms in Hebe. A hierarchical sequencing graph is used to model hardware behavior for synthesis. The hardware behavior is assumed to be synchronous and non-pipelined. As with other hardware models, both control-flow and data-flow dependencies are represented by the sequencing graph model. Its main distinction is that it uniformly supports concurrency, synchronization, and detailed timing constraints. Synthesis algorithms operating on this model can guarantee that the resulting design satisfies the imposed constraints, or indicate when no such solution exists. The use of this model decouples the synthesis algorithms from the HardwareC language. In particular, different hardware description languages can be supported by compiling them into this model. The Sequencing Intermediate Form is an ASCII representation of the sequencing graph which is used as an interchange format facilitating communication between different tools, i.e. the Vulcan partitioner [GM90] and Hebe both use the SIF format.
KeywordsHardware Resource Resource Model Combinational Logic Constraint Graph Loop Body
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