Experimental Results

  • David C. Ku
  • Giovanni De Micheli
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 177)


This chapter describes the experimental results and design experiences in using the Hercules and Hebe high-level synthesis programs. Several digital ASIC designs were synthesized using this system, including an Ethernet coprocessor [GC91], a Digital Audio input output (DAIO) chip [LBMG89], a bi-dimensional discrete cosine transform (BDCT) chip [RM89], a decoder chip for the space telescope [Kas89], a raster line drawing design, an error-correcting code design, and a greatest common divisor design. Each design was described completely in HardwareC and synthesized to a logic-level implementation. Extensive logic-level simulation demonstrated the correctness of the specification and implementation.


Direct Memory Access Synthesis Result Area Cost Simulation Trace Critical Path Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 1992

Authors and Affiliations

  • David C. Ku
    • 1
  • Giovanni De Micheli
    • 2
  1. 1.Redwood Design AutomationStanford UniversityUSA
  2. 2.Stanford UniversityUSA

Personalised recommendations