Structural VHDL

Abstract

This chapter discusses the structural style of VHDL. It contains the following sections:

• Component Instantiation Using Named Notation

• Generate Statement

• Configurations

Generics The VHDL structural style describes the interconnection of components within an architecture. It is similar to a netlisting language in other CAD systems. In a structural architecture, you declare the components that you are using, then create instances of those components with particular mappings of signal wires to the various pins of the components. Each component instantiation is a concurrent statement similar to those described in Chapter 6.