VHDL Structure & Syntax

  • Stanley Mazor
  • Patricia Langstraat

Abstract

This chapter diagrams VHDL design hierarchy, structure, and VHDL language syntax. It is organized into the following sections:
  • Design Hierarchy

  • Library Units

  • Declarations

  • Specifications

  • Use & Library Clauses

  • Sequential Statements

  • Concurrent Statements

  • Predefined Attributes

  • Package STANDARD

  • TEXTIO Package

Keywords

Sequential Statement Assertion Statement Concurrent Statement Array Object Interface Port 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media Dordrecht 1992

Authors and Affiliations

  • Stanley Mazor
    • 1
  • Patricia Langstraat
    • 1
  1. 1.Synopsys, Inc.USA

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