Abstract
The development of advanced BiCMOS processes has given the design engineer new flexibility with regards to basic digital design techniques. Conventional TTL, ECL, and CMOS technologies each have intrinsic strengths and weaknesses and thus each has established suitable applications in both standard “glue” logic as well as the newer application specific markets. BiCMOS technology allows fabrication of monolithic circuits which use all of the above design techniques as well as new hybrid BiCMOS circuits which take advantage of the strengths of the individual technologies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
David A. Hodges and Horace G. Jackson, “Analysis and Design of Digital Integrated Circuits”, McGraw Hill, 1983.
Lance A. Glasser and Daniel W. Dobberpuhl, “The Design and Analysis of VLSI Circuits”, Addison Wesley, 1985.
Motorola BiMOS Macrocell Array Design Manual, 1988.
Hiroshi Nakashiba, Kaszuyoshi Yamada, Tsutomo Hatano, Akira Denda, Norio Kusonose, Eigo Fuse, and Masakazu Sasaki, “A Subnanosecond Bi-CMOS Gate-Array Family”, IEEE CICC, 1986.
Takahide Ikeda, Atsuo Watanabe, Yoji Nishio, Ikuro Masuda, Nobuo Tamba, Masanori Odaka, and Katsumi Ogiue, “High-Speed BiCMOS Technology with a Buried Twin Well Structure”, IEEE Transactions on Electron Devices, Vol. ED-34, No. 6, pp. 1304–1309, 1987.
AMCC Q14000 Series BiCMOS Logic Arrays Preliminary Device Specification, Macrocell Array Design Manual, 1988.
Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watanabe, Shoji Shukuri, Katsuhiro Shimohigashi, “A BiCMOS Logic Gate with Positive Feedback”, IEEE ISSCC, Vol 32, pp. 116–117, 1989.
Paul R. Gray, and Robert G. Meyer, “Analysis and Design of Integrated Circuits”, John Wiley, 1977.
A.R. Alvarez, J. Arreola, S.Y. Pai, K.N. Ratnakumar, “A Methodology for Worst-Case Design of BiCMOS Integrated Circuits”, BCTM, PP. 172–175, 1988.
A.R. Alvarez, “BiCMOS vs. CMOS Buffers”, Internal Correspondence, October, 1987.
G.P. Roseel, R.W. Dutton, K. Mayaram, and D.O. Pederson, “Delay Analysis for BiCMOS Drivers”, BCTM, pp. 220–222, 1988.
E.W. Greenich, K.L. McLaughlin, “Analysis and Characterization of BiCMOS for High Speed Digital Logic”, IEEE J. Solid State Circuits, Vol. SC-23, no. 2, pp. 566–572, April 1988.
Richard S. Muller and Theodore I. Kamins, “Device Electronics for Integrated Circuits”, John Wiley, pp. 244–287, 1977.
Jame McDonald, Rajnish Maini, Lou Spangler, and Skip Weed, “Response Surface Methodology; A Modeling tool for Integrated Circuit Designers”, IEEE CICC, pp 13.4.1–13. 4. 4, 1988.
A.R. Alvarez, J. Teplik, D.W. Schucker, T. Hulseweh, H.B. Liang, M. Dydyk, I. Rahim, “Second Generation BiCMOS Gate Array Technology”, Proceedings IEEE Bipolar Circuits and Technology Symposium, 1987.
BiCMOS, Is it the Next Technology Driver?”, Electronics, February 4, 1988.
A.R. Alvarez, D.W. Schucker, “BiCMOS Technology For Semi-Custom Integrated Circuits”, Proceedings of the CICC, 1988.
Anthony Wong, Alex Hui, Eric Chan, Dan Wong, Steve Chan, Bill Carney, “A High Density BiCMOS Direct Drive Array”, IEEE CICC, pp. 20.6.1–20. 6. 3, 1988.
P.S. Bennett, R.P. Dixon, F. Ormerod, “High Performance BIMOS Gate Arrays with Embedded Configurable Static Memory”, CICC, 1987.
F. Ormerod, D.W. Schucker, K. Deierling, N. Salamina, “A Mixed Technology Gate Array with ECL and BiMOS Logic on a Single Chip”, Symp. on VLSI Circuits, pp. 31–33, 1987.
Y. Kowase, “A BiCMOS Analog/Digital LSI with the Programmable 280bit SRAM”, ISSCC, 1986, PP. 170–173, 1985.
Yasuhiro Sugimoto, and Hiroyuki Hara,, “Bi—CMOS Interface Circuit In Mixed CMOS/TI’L and ECL Use Environment”, First International Symposium on BiCMOS, 1986.
S. P. Murarka, “Silicides for VLSI Applications”, Academic Press, 1983.
Yannis P. Tsividis, “Accurate Analysis of Temperature Effects in le—Vbe Characteristics with Application to Bandgap Reference Sources”, IEEE JSSC, Vol SC-15, no. 6, pp. 1076–1083, December 1980.
Fairchild F100K ECL Data Book, pp. 2–7, 1982.
R. Eden, J. Clark, A. Fiedler, F. Lee, “VBB Feedback Approach for Achieving ECL Compatibility in GaAs ICs”, Tech. Digest GaAs IC Symposium, pp. 123–127, 1986. Sources”, IEEE JSSC, Vol SC-15, no. 6, pp. 1076–1083, December 1980.
W. Heimsch, B. Hoffman, R.Krebs, E. Muellner, B. Pfaeffel, K. Ziemann, “Merged CMOS/Bipolar Current Switch Logic”, IEEE ISSCC, Vol 32, pp. 112–113, 1989.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1990 Springer Science+Business Media New York
About this chapter
Cite this chapter
Deierling, K. (1990). Digital Design. In: Alvarez, A.R. (eds) BiCMOS Technology and Applications. The Springer International Series in Engineering and Computer Science, vol 76. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2029-7_5
Download citation
DOI: https://doi.org/10.1007/978-1-4757-2029-7_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2031-0
Online ISBN: 978-1-4757-2029-7
eBook Packages: Springer Book Archive