BiCMOS Process Technology

  • R. A. Haken
  • R. H. Havemann
  • R. H. Eklund
  • L. N. Hutter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 76)

Abstract

For high performance LSI and VLSI digital circuit applications, BiCMOS technology has become predominantly driven from a CMOS processing base. The principle reason for this is that LSI and VLSI digital BiCMOS circuits tend to be CMOS-intensive because of power dissipation limitations (for example, high density ECL I/O SRAMs and gate arrays). The CMOS-intensive nature of these circuits requires a process technology that will result in the highest possible CMOS performance. Consequently, BiCMOS fabrication technology tends to be CMOSbased, and the process steps needed to realize a high performance bipolar device are usually merged with a core CMOS process flow [3.1, 3.2, 3.3]. In the case of analog BiCMOS, the increasing demand to have on-board digital logic integration has also resulted in these processes being CMOS-oriented.

Keywords

Gate Oxide Bipolar Transistor Gate Length NMOS Transistor CMOS Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 3.1]
    T. Ikeda, A. Wantanabe, Y. Nishio, I. Masuda, N. Tamba, M. Odaka and K. Ogiue, “High-speed BiCMOS technology with a buried twin-well structure,” IEEE Trans. Electron devices, vol. ED-34, pp. 1304–1309, June 1987.Google Scholar
  2. 3.2]
    B. Bastani, C. Lage, L. Wong, J. Small, L. Bouknight and T. Bowman, “Advanced one micron BiCMOS technology for high speed 256K SRAM”s,” Digest of Technical Papers, 1987 Symposium on VLSI Technology, pp. 41–42, May 1987.Google Scholar
  3. 3.3]
    R. Havemann, R. Eklund, R. Haken, D. Scott, H. Tran, P. Fung, T. Ham, D. Favreau and R. V irkus, “An 0.8 µm 256K BiCMOS SRAM technology,” Digest of Technical Papers, 1987 International Electron devices Meeting, pp. 841–843, December 1987.Google Scholar
  4. 3.4]
    M-L. Chen, C-W. Leung, W. Cochran, R. Harney, A. Maury and H. Hey, “A high performance submicron CMOS process with self-aligned channel-stop and punchthrough implants,” Digest of Technical Papers, 1986 International Electron Devices Meeting, pp. 256–259, December 1986.Google Scholar
  5. 3.5]
    R. Chapman, R. Haken, D. Bell, C. Wei, R. Havemann, T. Tang, T. Holloway and R. Gale, “An 0.8 µm CMOS technology for high performance logic applications,” Digest of Technical Papers, 1987 International Electron Devices Meeting, pp. 362–365, December 1986.Google Scholar
  6. 3.6]
    J. Miyamoto, S. Saito, H. Momose, H. Shibata, K. Kanzaki and S. Kohyama, “A 1 gm n-well/bipolar technology for VLSI circuits,” Digest of Technical Papers, 1983 International Electron Devices Meeting, pp. 63–66, December 1983.Google Scholar
  7. 3.7]
    H. Higuchi, G. Kitsukawa, T. Ikeda, Y. Nishio, N. Sasaki and K. Ogiue, “Performance and structures of scaled-down bipolar devices merged with CMOSFETS,” Digest of Technical Papers, 1984 International Electron Devices Meeting, pp. 694–697, December 1984.Google Scholar
  8. 3.8]
    H. Tran, D. Scott, P. Fung, R. Havemann, R. Eklund, T. Ham, R. Haken and A. Shah, “An 8 ns 256K ECL SRAM with CMOS memory array and battery backup capability”, IEEE J. Solid State Devices, vol. SC-23, pp. 1041–1047, October 1988.Google Scholar
  9. 3.9]
    R. de Werdt, P. van Attekum, H. den Blanken, L. de Bruin, F. op den Buijsch, A. Burgmans, T. Doan, H. Godon, M. Grief, W. Jansen, A. Jonkers, F. Klaassen, M. Pitt, P. van der Plas, A. Stolmeijer, R. Verhaar and J. Weaver, “A 1M SRAM with full CMOS cells fabricated in a 0.7 p.m technology”, Digest of Technical Papers, 1987 International Electron Devices Meeting, pp. 532–535, December 1987.Google Scholar
  10. 3.10]
    H-J. Bohm, L. Bemewitz, W. Bohm and R. Kopl, “Megaelectronvolt phosphorus implantation for bipolar devices,” IEEE Trans. Electron Devices, vol. ED-35, no. 10, pp. 1616–1619, October 1988.CrossRefGoogle Scholar
  11. 3.11]
    J. Borland, M. Gangani, R. Wise, S. Fong, Y. Oka and Y. Matsumoto, “Siliconepitaxial growth for advanced device structures,” Solid State Technology, pp. 111–119, January 1988.Google Scholar
  12. 3.12]
    R. Herring, “Advances in reduced pressure silicon epitaxy,” Solid State Technology, pp. 75–80, November 1979.Google Scholar
  13. 3.13]
    M. Graef and B. Leunissen, “Antimony, arsenic, phosphorus, and boron autodoping in silicon epitaxy,” J. Electrochem. Soc., vol. 132, no. 8, pp. 1942–1954, August 1985.CrossRefGoogle Scholar
  14. 3.14]
    G. Srinivasan, “Kinetics of lateral autodoping in silicon epitaxy,” J. Electrochem. Soc., vol. 125, no. 1, pp. 146–151, January 1978.CrossRefGoogle Scholar
  15. 3.15]
    R. Rung, H. Momose and Y. Nagakubo, “Deep trench isolated CMOS devices,” Digest of Technical Papers, 1982 International Electron Devices Meeting, pp. 237–240, December 1982.Google Scholar
  16. 3.16]
    C. Teng, C. Slawinski and W. Hunter, “Defect generation in trench isolation,” Digest of Technical Papers, 1984 International Electron Devices Meeting, pp. 586–589, December 1984.Google Scholar
  17. 3.17]
    S. Suyama, T. Yachi and T. Serikawa, “A new self-aligned well-isolation technique for CMOS devices,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1672–1677, November 1986.Google Scholar
  18. 3.18]
    N. Kasai, N. Endo, A. Ishitani and H. Kitajima, “1/4 p.m CMOS isolation technique using selective epitaxy,” IEEE Trans. Electron Devices, vol. ED-34, pp. 1331–1336, June 1987.Google Scholar
  19. 3.19]
    K. Cham, S. Chiang, D. Wenocur and R. Rung, “Characterization and modeling of the trench surface inversion problem for the trench isolated CMOS technology,” Digest of Technical Papers, 1984 International Electron Devices Meeting, pp. 23–26, December 1983.Google Scholar
  20. 3.20]
    J. Brighton, D. Verret, T. Ten Eyck, M. Welch, R. McMann, M. Torreno, A. Appel, M. Keleher, “Scaling issues in the evolution of ExCL bipolar technology,” Digest of Technical Papers, IEEE 1988 Bipolar Circuits Technology Meeting, pp. 121–124, September 1988.Google Scholar
  21. 3.21]
    K. Chiu, J. Moll and J. Manoliu, “A bird”s beak free local oxidation technology feasible for VLSI circuits fabrication,” IEEE Trans. Electron Devices, vol. ED-29, pp. 536540, April 1982.Google Scholar
  22. 3.22]
    K. Wang, S. Sailer, W. Hunter, P. Chatterjee and P. Yang, “Direct moat isolation for VLSI,” IEEE Trans. Electron Devices, vol. ED-29, pp. 541–547, April 1982.Google Scholar
  23. 3.23]
    N. Matsukawa, H. Nozawa, J. Matsunaga and S. Kohyama, “Selective polysilicon oxidation technology for VLSI isolation,” IEEE Trans. Electron Devices, vol. ED-29, pp. 561–573, April 1982.Google Scholar
  24. 3.24]
    A. Alvarez, P. Meller, D. Schucker, F. Ormerod, J. Teplik, B. Tien and D. Maracas, “Technology considerations in BI-CMOS integrated circuits,” International Conference on Computer Design, pp. 159–163, 1985.Google Scholar
  25. 3.25]
    T. Ning, P. Cook, R. Denard, C.Osbum, S. Schuster and H. Yu, “1 p.m MOSFET VLSI technology: Part-IV–Hot electron design constraints,” IEEE Trans. Electron Devices, vol. ED-26, pp. 346–353, 1979.Google Scholar
  26. 3.26] S. Ogura, P. Tsang, W. Walker, D. Critchlow, and J. Shepard, “Design and characteristics of the lightly doped drain source (LDD)
    insulated gate field effect transistor,” IEEE Trans. Electron devices, vol. ED-27, pp. 1359–1367, 1980.Google Scholar
  27. 3.27]
    H. Katto, K. Okuyama, S. Meguro, R. Nagai, and S. Ikeda, “Hot carrier degradation modes and optimization of LDDMOSFETS,”Digestof Technical Papers, 1984 International Electron Devices Meeting, pp. 774–777, December 1984.Google Scholar
  28. 3.28]
    K. Balasubramanyam, M. Hargrove, H. Hanafi, M. Lin, and D. Hoyniak, “Characterization of As-P double diffused drain structure,”Digestof Technical Papers, 1984 International Electron Devices Meeting, pp. 782–785, December 1984.Google Scholar
  29. 3.29]
    S. Meguro, S. Ikeda, K. Nagasawa, A. Koike, T. Yasui, Y. Sakai and T. Hayashida, “Hi-CMOS III technology,” Digest of Technical Papers, 1984 International Electron Devices Meeting, pp. 59–62, December 1984.Google Scholar
  30. 3.30]
    H. Nakashiba, I. Ishida, K. Aomura, and T. Nakamura, “An advanced PSA techology for high-speed bipolar LSI,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1390–1394, August 1980.Google Scholar
  31. 3.31]
    Y. Kobayashi, M. Oohayashi, K. Asayama, T. Ikeda, R. Hori and K. Itoh, “Bipolar CMOS merged structure for high speed M bit DRAM,” Digest of Technical Papers, 1986 International Electron Devices Meeting, pp. 802–804, December 1986.Google Scholar
  32. 3.32]
    M. Brassington, M. El-Diwany, P. Tuntasood and R. Razouk, “An advanced submicron BiCMOS technology for VLSI applications,” Digest of Technical Papers, 1988 Symposium on VLSI technology, pp. 89–90, May 1988.Google Scholar
  33. 3.33]
    K. Rajkanan, T. Gheewala and J. Diedrick, “A high-performance B iCMOS technology with double-polysilicon self-aligned bipolar devices,” IEEE Electron Device Letters, vol. EDL-8, pp. 509–511, November 1987.Google Scholar
  34. 3.34]
    T. Yuzuriha, T. Yamaguchi and J. Lee, “Submicron Bipolar-CMOS technology using 16 GHz fT double-polysilicon bipolar devices,” Digest ofTechnical Papers, 1988 International Electron Devices Meeting, pp. 748–751, December, 1988.Google Scholar
  35. 3.35]
    G. Kitsukawa, R. Hori, Y. Kawajiri, T. Watanabe, T. Kawahara, K. Itoh, Y. Kobayashi, M. Oohayashi, K. Asayama, T. Ikeda and H. Kawamoto, “An Experimental 1-Mbit BìCMOS DRAM,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 657–662, October 1987.Google Scholar
  36. 3.36]
    E. Chor, P. Ashburn and A. Brunnschweiler, “Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors,” IEEE Electron Device Letters, vol. EDL6, pp. 516–518, October 1985.Google Scholar
  37. 3.37]
    P. Ashburn, D. Roulston and C. Selvakumar, “Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-34, pp. 1346–1353, June 1987.Google Scholar
  38. 3.38]
    B. Landau, B. Bastani, D. Haueisen, R. Lahri, S. Joshi, and J. Small, “Poly emitter bipolar transistor optimization for an advanced BiCMOS technology,” Digest of Technical Papers, 1988 IEEE Bipolar Circuits andTechnology Meeting, pp. 117–119, September 1988.Google Scholar
  39. 3.39]
    H. Park, K. Boyer, C. Clawson, G. Eiden, A. Tang, T. Yamaguchi, and J. Sachitano, “High-speed polysilicon emitter-base bipolar transistor,” IEEE Electron Device Letters, vol. EDL-7, pp. 658–660, December 1986.Google Scholar
  40. 3.40]
    E. Greeneich and K. McLaughlin, “Analysis and characterization of BiCMOS for highspeed digital logic,” IEEE J. Solid-State Circuits, vol. 23, pp. 558–565, April 1988.CrossRefGoogle Scholar
  41. 3.41]
    R. Chapman, D. Bell, R. Eklund, R. Havemann, M. Harward and R. Haken, “Submìcron BiCMOS well design for optimum circuit performance,” Digest of Technical Papers, 1988 International Electron Devices Meeting, pp. 756–759, December 1988.Google Scholar
  42. 3.42]
    T. Ikeda, A. Watanabe, Y. Nishio, I. Masuda, N. Tamba, M. Odaka and K. Ogiue, “High-speed BiCMOS technology with a buried twin well structure,” IEEE Trans. Electron Devices, vol. ED-34, pp. 1304–1310, June 1987.Google Scholar
  43. 3.43]
    D. Tang and P. Solomon, “Bipolar transistor design for optimized power-delay logic circuits,” IEEE Journal of Solid-State Circuits, vol. SC-14, pp. 679–684, August 1979.Google Scholar
  44. 3.44]
    S. Konaka, Y. Amemiya, K. Sakuma and T. Sakai, “A 20 ps/G Bipolar IC using advanced SST with collector ion implantation,” Extended Abstracts of the 19th Conference on Solid State Devices and Materials, pp. 331–334, 1987.Google Scholar
  45. 3.45]
    D. Scott, W. Hunter and H. Shichijo, “A new transmission line model for silicided source/drain diffusions: Impact on VLSI circuits,” IEEE Trans. Electron Devices, vol. ED-29, pp. 651–661, April 1982.Google Scholar
  46. 3.46]
    M. Alperin, T. Holloway, R. Haken, C. Gosmeyer, R. Karnaugh and W. Parmantie, “Development of the self-aligned titanium silicide process for VLSI applications,” IEEE Trans. Electron devices, vol. ED-32, pp. 141–149, February 1985.Google Scholar
  47. 3.47]
    C. Lau, Y. See, D. Scott, J. Bridges, S. Perna and R. Davies, “Titanium disilicide self-aligned source/drain and gate technology,” Digest of Technical Papers, 1982 International Electron Devices Meeting, pp. 774–777, December 1982.Google Scholar
  48. 3.48]
    R. Haken, “Application of the self-aligned titanium silicide process to VLSI NMOS and CMOS technologies”, J. Vac. Sci. Technol. B 3 (6), pp. 1657–1663, Nov/Dec. 1985.Google Scholar
  49. 3.49]
    D. Scott, R. Chapman, C. Wei, S. Mahant-Shetti, R. Haken and T. Holloway, ‘Titanium disilicide contact resistivity and its impact on 1 µm CMOS circuit performance,” IEEE Trans. Electron Devices, vol. ED-34, pp. 562–574, March 1987.Google Scholar
  50. 3.50]
    T. Tang, C. Wei, R. Haken, T. Holloway, L Hite and T. Blake, ‘Titanium nitride local interconnect technology for VLSI,” IEEE Trans. Electron Devices, vol. ED-34, pp. 682–688, March 1987.Google Scholar
  51. 3.51]
    O. Kudoh, H. Ooka, I. Sakai, M. Saitoh, J. Ozaki and M. Kikuchi, “A new full CMOS SRAM cell structure,” Digest of Technical Papers, 1984 International Electron Devices Meeting, pp. 67–70, December 1984.Google Scholar
  52. 3.52]
    C. Kaanta, W. Cote, J. Cronib, K. Holland, P. Lee and T. Wright, “Submicron wiring technology with tungsten and planarization, ’ Digest of Technical Papers, 1987 International Electron Devices Meeting, pp. 67–70, December 1987.Google Scholar
  53. 3.53]
    T. Bonifield, R. Gale, B. Shen, G. Smith and C. Huffman, “A 1 micron design rule double level metallization process,” Proceedings of the IEEE 1986 VLSI Multilevel Interconnection Conference, pp. 71–77, June 1986.Google Scholar
  54. 3.54]
    T. Bonifield, S. Crank, R. Gale, J. Graham, C. Huffman, B. Jucha, G. Smith, M. Yao, S. Aoyama, Y. Imamura, K. Hamamoto, H. Kawasaki, T. Kaeriyama, Y. Miyai, M. Nishimura and M. Utsugi, “A 2 micron pitch triple level metal process using CVD tungsten”, Digest ofTechnical Papers, 1988 Symposium on VLSlTechnology, pp. 101–102, May 1988.Google Scholar
  55. 3.55]
    T. Yuzuriha and S. Early, “Failure mechanisms in a 4 micron pitch gold IC metallization process,” Proceedings of the IEEE 1986 VLSI Multilevel Interconnection Conference, pp. 146–152, June 1986.Google Scholar
  56. 3.56]
    C. Hu, S. Chang, M. Small and J. Lewis, “Diffusion barrier studies for copper,” Proceedings of the IEEE 1986 VLSI Multilevel Interconnection Conference, pp. 181–184, June 1986.Google Scholar
  57. 3.57]
    A. Alvarez, P. Meller and B. Tien, “2 micron merged bipolar-CMOS technology,” Digest of Technical Papers, 1984 International Electron Devices Meeting, pp. 761–764, December 1984.Google Scholar
  58. 3.58]
    M. Polinsky and S. Graf, “MOS-Bipolar monolithic integrated circuit technology,” IEEE Trans. Electron Devices, vol. ED-20, pp. 239–244, March 1973.Google Scholar
  59. 3.59]
    M. Polinsky, O Schade Jr. and J. Keller, “CMOS-Bipolar monolithic integrated-circuit technology,” Digest of Technical Papers, 1973 International Electron Devices Meeting, pp. 229–231, December 1973.Google Scholar
  60. 3.60]
    H. Lin, “Comparison of input offset voltage of differential amplifiers using bipolar transistors and field-effect transistors,” IEEE J. Solid-State Circuits, vol. SC-5, pp. 126–129, June 1970.Google Scholar
  61. 3.61]
    H. De Man, R. Vanparys and R. Cuppens, “A low input capacitance voltage follower in a compatible silicon-gate MOS-Bipolar technology,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 217–223, June 1977.Google Scholar
  62. 3.
    ] “Si-gate CMOS programmable op amps rival bipolars,” Electronic Products, p. 34, March 4, 1983.Google Scholar
  63. 3.63]
    E. Snow and B. Deal, “Polarization phenomena and other properties of phosphosilicate glass films on silicon,” J. Electrochem. Society, vol. 113, no. 3, pp. 263–269, March 1966.CrossRefGoogle Scholar
  64. 3.64]
    S. Miller, “Advances in process development lead to new architectures in data converters,” Electro ‘83, pp. 1–5, April 1983.Google Scholar
  65. 3.65]
    T. Lindenfelser, D. Fertig, M. Schmidt and K. Perttula, “A 12-volt analog/digital BiCMOS process,” IEEE Proceedings of Bipolar Circuits and Technology Meeting, pp. 184–187, 1987.Google Scholar
  66. 3.66]
    K. Sato, K. Shimizu, Y. Nakamura, K. Oka, F. Nakamura and T. Kimura, “A novel BiCMOS technology with upward and downward diffusion technique,” Electronics and Communication in Japan, Part 2, vol. 69, no. 7, pp. 1–8, 1986.CrossRefGoogle Scholar
  67. 3.67]
    S. Weber, “TI soups up LinCMOS process with 20-V bipolar transistors,” Electronics, Feb. 4, 1988, pp. 59–60.Google Scholar
  68. 3.68]
    T. Guy and D. Grant, “Complete DAC chip weds true monotonicity to 16-bit resolution,” Electronic Design, June 14, 1984, pp. 273–282.Google Scholar
  69. 3.69]
    P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, pp. 116–117, New York: Wiley 1984.Google Scholar
  70. 3.70]
    M. Nanba, T. Shiba, T. Nakamura and T. Toyabe, “An analytical and experimental investigation of the cutoff frequency Ft of high-dpeed bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-35, pp. 1021–1028, July 1988.Google Scholar
  71. 3.71]
    R. Troutman, “VLSI limitiations from drain-induced barrier lowering,” IEEE Trans. Electron Devices, vol. ED-27, pp. 461–468, April 1979.Google Scholar
  72. 3.72]
    P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, pp. 389394 and pp. 705–9, New York: Wiley, 1984.Google Scholar
  73. 3.73]
    H. Katto, Y. Kamigaki and Y. Itoh, “MOSFET’s with reduced low frequency 1/f noise,” Proc. 6th Conference on Solid State Devices, pp. 243–248, Tokyo, 1974.Google Scholar
  74. 3.74]
    A. Grove, Physics and Technology of Semiconductor Devices, pp. 230–234, New York: Wiley, 1967.Google Scholar
  75. 3.75]
    C. Anagnostopoulos, P. Zeitzoff, K. Wong and B. Brandt, An isolated vertical npn bipolar transistor in an n-well CMOS process, Digest ofTechnical Papers, 1984International Electron Devices Meeting, pp. 588–593, December 1984.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • R. A. Haken
    • 1
  • R. H. Havemann
    • 1
  • R. H. Eklund
    • 1
  • L. N. Hutter
    • 1
  1. 1.Texas Instruments, Inc.USA

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