BiCMOS technology combines Bipolar and CMOS transistors in a single integrated circuit. By retaining the benefits of Bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously unattainable with either technology individually. CMOS technology maintains an advantage over Bipolar in power dissipation, noise margins, packing density, and the ability to integrate large complex functions with high yields. Bipolar technology has advantages over CMOS in switching speed, current drive per unit area, noise performance, analog capability, and I/O speed. This last point is especially significant given the growing importance of ECL I/O, historically the exclusive domain of Bipolar technology, for high speed systems [1.1]. It follows that BiCMOS technology offers the advantages of: 1) improved speed over CMOS, 2) lower power dissipation than Bipolar (which simplifies packaging and board requirements), 3) flexible I/Os (TTL, CMOS, or ECL), 4) high performance analog, and 5) latchup immunity [1.2]. Compared to CMOS, the reduced dependence on capacitive load and process/temperature variations, and the multiple circuit configurations and I/Os possible with BiCMOS greatly enhance design flexibility and can lead to reduced design cycle time. The inherent robustness of BiCMOS with respect to temperature and process variations also reduces the variability of final electrical parameters resulting in a higher percentage of prime units, an important economic consideration.


Power Dissipation CMOS Technology Gate Oxide Solid State Circuit Capacitive Load 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.1]
    A.R. Alvarez, P. Meiler, B. Tien, “2 µm Merged BIMOS Technology,” 1984 Int. Electron Devices Meeting, pp. 420–424.Google Scholar
  2. 1.2]
    A.R. Alvarez, D.W. Schucker, “BiCMOS Technology for Semi-Custom Integrated Circuits,” Cust. Int. Cir. Conf., pp. 22.1.1–22. 1. 5, 1988.Google Scholar
  3. 1.3]
    H. G. Lin, J.C. Ho, R.R. Iyer, K. Kwong, “Complementary MOS-Bipolar Transistor Structure,” IEEE Trans. Electron Devices, Vol. ED-16, No. 11, Nov. 1969, pp. 945–951.Google Scholar
  4. 1.4]
    M.A. Polinsky, O.H. Schade, J.P. Keller, “CMOS-Bipolar Monolithic Integrated Circuit Technology,” 1973 Int. Electron Devices Meeting, pp. 229–231.Google Scholar
  5. 1.5]
    J. D. Plummer, J.D. Meindl, “A Monolithic 200-V CMOS Analog Switch,”J. Solid State Circuits, SC-11, No. 6, Dec. 1976, pp. 809–817.Google Scholar
  6. 1.6]
    S. Davis, “Simplified Driver, New Applications Spur Plasma-Panel Usage,” Electronic Design News, Sept. 20, 1979, pp. 51–55.Google Scholar
  7. 1.7]
    B. Holland, D.P. Peppenger, “Single-Chip Linear Regulator Handles 125V I/O Differential,” Electronic Design, Sept. 17, 1981, pp. 129–133.Google Scholar
  8. 1.8]
    T.E. Ruggles, G.V. Fay, “Mixed Process Puts High Power Under Control,” Electronic Design, Vol$130, No. 7, March 31, 1982, pp. 69–77.Google Scholar
  9. 1.9]
    A.R. Alvarez, R.M. Roop, K.I. Ray, G. R. Gettemeyer, “Lateral DMOS Transistor Optimized for High Voltage BiCMOS Applications,” 1983 Int. Electron Devices Meeting, pp. 420–423.Google Scholar
  10. 1.10]
    S. Lytle, R. Roop, D. Cave, D. Hughes, W. Gegg, A.R. Alvarez, “Power BiCMOS - A Versatile IC Technology for Switching and Regulation Applications”, 1984 Custom Integrated Circuits Conference, pp. 51–56.Google Scholar
  11. 1.11]
    E.J. Wildi, T.P. Chow, M.S. Adler, M.E. Cornell, G.C. Pifer”, New High Voltage IC Technology”, 1984 Int. Electron Devices Meeting pp. 262–265.Google Scholar
  12. 1.12]
    R.T. Gallager, “Single Chip Carries Three Technologies,” Electronics Week, Dec. 10, 1984, p. 28.Google Scholar
  13. 1.13]
    H. Higuchi, G. Kitsukawa, T. Ikeda, Y. Nishio, “Performance and Structures of Scaled-Down Bipolar Devices Merged with CMOSFETs,” Int. Electron Devices Meeting, p. 694–697, 1984.Google Scholar
  14. 1.14]
    J. Miyamoto, S. Saitoh, H. Momose, H. Shibata, K. Kanzaki, S. Kohyama,” A N-Well CMOS/ Bipolar Technology For VLSI Circuits”, 1984 Int. Electron Devices Meeting, pp. 63–66.Google Scholar
  15. 1.15]
    B. Bastani, C. Lage, L. Wong, J. Small, R. Lahri, L. Bouknight, T. Bowman, J. Manoliu, P. Tuntasood, “Advanced lµ BiCMOS Technology for High Speed 256K SRAMs,” 1987 Symp. on VLSI Technology, pp. 41–42.Google Scholar
  16. 1.16]
    N. Tamba S. Miyaoka, M. Odaka, M. Hirao, K. Ogiue, K. Tamada, T. Ikeda, H. Higuchi, H. Uchida, “An 8ns 256K BiCMOS SRAM,” 1988 Int. Solid State Circuits Conference, pp. 184–185.Google Scholar
  17. 1.17]
    A.R. Alvarez, J. Teplik, D.W. Schucker, T. Hulseweh, H.B. Liang, M. Dydyk, I. Rahim, “Second Generation BiCMOS Gate Array Technology,” 1987 Bipolar Circuits and Technology Meeting, pp. 113–117.Google Scholar
  18. 1.18]
    T. Hotta, I. Masuda, H. Maejima, A. Hotta, “CMOS/Bipolar Circuits for 60MHz Digital Processing,” 1986 Int. Solid State Circuits Conference, pp. 190–191.Google Scholar
  19. 1.19]
    A.R. Alvarez, J. Teplik, H.B. Liang, T. Hulseweh, D.W. Schucker, K.L. McLaughlin, K.A. Hansen, B. Smith, “VLSI BiCMOS Technology and Applications,” 1987 International Symp on VLSI Technology, Systems, and Applications, pp. 314–319.Google Scholar
  20. 1.20]
    M.P. Brassington, M. El-Diwany, P. Tuntasood, R.R. Razouk, “An Advanced Submicron BiCMOS Technology for VLSI Applications,” 1988 Symp. on VLSI Technology, pp. 89–90.Google Scholar
  21. 1.21]
    M. Kubo, “Perspective on BiCMOS VLSIs,” Symp. VLSI Technology Dig. Tech. Papers, pp. 89–90, 1987. Also in IEEE J. Solid State Circuits, Vol. SC-23, No. 1, Feb. 1988, pp. 5–11.Google Scholar
  22. 1.22]
    B.L. Morris, “BiCMOS Digital Design Techniques and Applications,” IEDM BiCMOS Technology and Design Short Course, 1987.Google Scholar
  23. 1.23]
    C. Sodini, S.S. Wong, P.K. Ko, “A Framework to Evaluate Technology and Device Enhancements for MOS Integrated Circuits,” IEEE J. Solid State Circuits, Vol. SC-24, No. 1, Feb. 1989, pp. 118–127.CrossRefGoogle Scholar
  24. 1.24]
    H.J. Bohm, L. Bernewitz, W.R. Bohm, R. Kopl, “Megaelectronvolt Phosphorus Implantation for Bipolar Devices,” IEEE Trans. Electron Devices, Vol. ED-35, No. 10, Oct. 1988, pp. 945–951.Google Scholar
  25. 1.25]
    R.C. Lutz, Aspen Semiconductor Corp., Private Communication, 1988.Google Scholar
  26. 1.26]
    T.Y. Chiu, et al, “A High Speed Super Self-Aligned Bipolar-CMOS Technology,” Int. Electron Device Meeting, pp. 24–27, 1987.Google Scholar
  27. 1.27]
    T. Yuzuriha, T. Yamaguchi, J. Lee, “Submicron Bipolar-CMOS Technology Using 16 GHz Ft Double Poly-Si Bipolar Devices,” Int. Electron Device Meeting, pp. 748–751, 1988Google Scholar
  28. 1.28]
    K. Shibayama, Y. Akasaka, “Laboratory and Factory Automation for ULSI Development and Mass Production,” Int. Electron Device Meeting, pp. 736–739, 1988.Google Scholar
  29. 1.29]
    R.A. Chapman, C.C. Wei, D.A. Bell, S. Aur, G.A. Brown, R.A. Haken, “0.5 Micron CMOS for High Performance at 3.3V,” Int. Electron Device Meeting, pp. 52–55, 1988.Google Scholar
  30. 1.30]
    B. Cole, “Aspen Shows BiCMOS Can Yield Fast SRAMs,” Electronics pp. 88, Feb. 1989.Google Scholar
  31. 1.31]
    H.V. Tran, D.B. Scott, K. Fung, R. Havemann, R.E. Eklund, T.E Ham, R.A. Haken, A.H. Shah, “An 8ns Battery Backup Submicron BiCMOS 256K ECL SRAM,” Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 188–189, 1988.Google Scholar
  32. 1.32]
    R.A. Kurtis, D.D. Smith, T.L. Bowman, “A 12ns 256K BiCMOS sRAM,” Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 186–187, 1988.Google Scholar
  33. 1.33]
    M. Matsui, H. Momose, Y. Urakawa, T. Maeda, A. Suzuki, N. Urakawa, K. Sato, K. Makita, J. Matsunaga, K. Ochii, “An 8ns 1Mb ECL BiCMOS SRAM,” Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 38–39, 1989.Google Scholar
  34. 1.34]
    H.V. Tran, K. Fung, D. Bell, R. Chapman, M. Harward, T. Suzuki, R. Havemann, R.Eklund, R. Fleck, D. Le, C. Wei, N. Iyengar, M. Rodder, R.A. Haken, D.B. Scott, “An 8ns 1MB ECL SRAM with a Configurable Memroy Array Size,” Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 36–37, 1989.Google Scholar
  35. 1.35]
    M. Suzuki, S. Tachibana, A. Watanabe, S. Shukuri, H. Higuchi, T. Nagano, K. Shimohigashi, “A 3.5ns/500mW 16Kb BiCMOS ECL RAM,” Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 32–33, 1989.Google Scholar
  36. 1.36]
    P.T. Hickman, F. Ormerod, D.W. Schucker, “A High Performance 6000 Gate BIMOS Logic Array,” Custom Int. Circuit Conference, pp. 562–564, 1986.Google Scholar
  37. 1.37]
    B. Cole, “Now There’s More Than Just Raw Speed in The ECL Arena,” Electronics, pp. 84–87, Feb. 1989.Google Scholar
  38. 1.38]
    P. Bosshart, “Introduction to Microprocessor Design,” Int. Electron Device Meeting Short Course, 1988.Google Scholar
  39. 1.39]
    T. Hotta, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi, “A 70Mhz 32b Microprocessor with 1.0µm BiCMOS Macrocell Library„“ Int. S.lid State Circuits Conf. Dig. Tech. Papers, pp. 124–125, 1989.Google Scholar
  40. 1.40]
    H. Momose et al, “0.5µm BiCMOS Technology,” Int. Electron Device Meeting, pp. 838–840, 1988.Google Scholar
  41. 1.41]
    H. Fukuda, S. Horiguchi, M. Urano, K. Fukami, K. Matsuda, N. Ohwada, H. Akiya, “A BiCMOS Channelless Masterslice with On-Chip Voltage Converter,” Ina. Solid State Circuits Conf. Dig. Tech. Papers, pp. 176–177, 1989.Google Scholar
  42. 1.42]
    W. Heimsch, B. Hoffmann, R. Krebs, E. Muellener, B. Pfaeffel, K. Ziemann, “Merged CMOS/Bipolar Current Switch Logic,”Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 112–1133, 1989.Google Scholar
  43. 1.43]
    Y. Nishio, F. Murabayashi, S. Kotoku, A. Watanabe, S. Shukuri, K. Shimohigashi, “A BiCMOS Logic Gate with Positive Feedback,” Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 116–117, 1989.Google Scholar
  44. 1.44]
    J.A. Coriale, W.C. Holton, (Eds), “Submicron BiCMOS Technology for the 90s,” SRC Topical Research Conference, Dec. 10–11, 1087. N. Anatha “BiCMOS Roadmap”.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • A. R. Alvarez
    • 1
  1. 1.Aspen Semiconductor Corp.USA

Personalised recommendations