Abstract
This chapter describes the defect models used in our research. These models perform two functions. First, the models provide a geometrical abstraction of local defects. In other words, defects are modeled as geometrical modifications to the specified layout geometry. Second, the models describe how layout geometry combines to form circuit faults. This information can then be used in the fault analysis phase.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1987 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Walker, D.M.H. (1987). Defect Models. In: Yield Simulation for Integrated Circuits. The Springer International Series in Engineering and Computer Science, vol 33. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-1931-4_3
Download citation
DOI: https://doi.org/10.1007/978-1-4757-1931-4_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5201-1
Online ISBN: 978-1-4757-1931-4
eBook Packages: Springer Book Archive