Introduction

  • Ronald R. Troutman
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 13)

Abstract

Latchup is a key concern to bulk CMOS. It stems from parasitic bipolar transistors, which are structurally inherent to bulk CMOS. These transistors can be activated in various ways, and as CMOS technologies are scaled down, both in dimension and in circuit delay, this variety grows. Under certain conditions the activated transistors can dominate circuit behavior. However, with proper process and layout design, CMOS chips can be operated under relatively harsh conditions without ever encountering latchup. What is proper can vary with application — the type of chip, its performance, package, allowable cost, etc. This book will provide the insight — as well as some useful analysis, characterization, and avoidance techniques — for assessing what is proper in each application.

Keywords

Epitaxial Layer CMOS Technology Power Supply Voltage Bipolar Transistor Noise Immunity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1986

Authors and Affiliations

  • Ronald R. Troutman
    • 1
  1. 1.IBM CorporationUSA

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