Skip to main content
SpringerLink
Log in

Future Physical Environments and Concurrent Computation

  • Chapter
Book cover Concurrent Computations

Abstract

Using graph-based representations of computation problems [1]–[3], the communication function of a “pseudo-general purpose,” massively parallel computing environment is discussed to help define technology-focussed realizations of that communication function. Compatible computation problems are neither constrained to highly regular structures (such as systolic arrays and their generalizations [4]) nor extended to the globally non-deterministic behavior of many general purpose problems [5]. A fully distributed [6], data driven [7] computing environment is assumed, emphasizing the impact of communications on algorithm execution [8]. Evolution of such massively concurrent computing environments is necessary to sustain the growth of computing power as device technologies approach fundamental limits on dimensional scaling and higher device performance [9],[10].

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J. Zeman and G.S. Moschytz Systematic design and programming of signal processors using project management techniques, IEEE Trans. Acoust., Speech, Sig. Proc. vol. ASSP-31, pp. 1536–1549 (1983).

    Article  Google Scholar 

  2. S.K. Tewksbury, Hierarchically localized mapping of signal processing algorithms onto programmable DSP’s, to be published.

    Google Scholar 

  3. H.V. Jagadish, T. Kailath, J.A. Newkirk and R.G. Mathews On hardware description from block diagrams, Proc. 1984 Int. Conf. Acoust., Speech, Sig. Proc., pp. 8.4.1–8.4.4 (1984).

    Google Scholar 

  4. S-Y. Kung, K.S. Arun, R.J. Gal-Ezer and D.V. Bhaskar RaoWavefront array processor: language, architectures and applications, IEEE Trans. Comp., vol. C-31, pp. 1054–1066 (1982).

    Article  Google Scholar 

  5. M. Broy, A theory for non determinism,parallelism, communication and con-currency, Theoretical Computer Science, vol. 45, pp. 1–61 (1987).

    Article  Google Scholar 

  6. P.H. Enslow and T.G. Saponas, Distributed and decentralized control in fully distributed processing systems: a survey of applicable models, Techn. Report GIT-ICS-81/02, Georgia Inst. of Technol. (Feb 1981).

    Google Scholar 

  7. P.C. Trelevan, D.R. Brownbridge and R.P. Hopkins, Data-driven and demand-driven computer architectures, Comp. Surveys, vol. 14, pp. 93–143 (1982).

    Article  Google Scholar 

  8. D.B. Gannon and J. van Rosendale, On the impact of communication complexity on the design of parallel numerical algorithms,IEEE Trans. Comp., vol. C-33, pp. 1180–1194 (1984).

    Article  Google Scholar 

  9. J.D. Meindl, Ultra-large scale integration, IEEE Trans. Elect. Dev., vol. ED-31, pp. 1555–1561 (1984).

    Article  Google Scholar 

  10. R.W. Keyes, Fundamental limits in digital information processing, Proc. IEEE, vol. 69, pp. 267–278 (1981).

    Article  Google Scholar 

  11. R.C. Aubusson and I. Catt, Wafer-scale integration - a fault tolerant procedure, IEEE J. Solid-State Circuits, vol. SC-13, pp. 339–344 (1973).

    Google Scholar 

  12. T. Mangir, Sources of failure and yield improvement for RVLSI and WSI: Part I, Proc. IEEE, vol. 72, pp. 690–708 (1984).

    Article  Google Scholar 

  13. J.W. Greene and A. El Gamal, Configuuration of VLSI arrays in the presence of defects, J. ACM, vol. 31, pp. 694–717 (1984).

    Article  Google Scholar 

  14. J.I. Raffel, et al., A wafer-scale integrator using restructurable VLSI, IEEE Trans. Elect. Dev., vol. ED-32, pp. 479–486 (1986).

    Google Scholar 

  15. W.R. Moore and M.J. Day, Yield-enhancement of a large systolic array chip,Microelectronic Reliability, vol. 24, pp. 511–526 (1984).

    Article  Google Scholar 

  16. T. Leighton and C.E. Leiserson, Wafer-scale integration of systolic arrays, IEEE Trans. Comp., vol. C-34, pp. 448–461 (1981).

    Article  Google Scholar 

  17. C.D. Chesley, Main memory wafer-scale integration, VLSI Design, vol. 6(3), pp. 54–58 (1985).

    Google Scholar 

  18. R.K. Spielberger, et al., Silicon-on-silicon packaging,IEEE Trans Compon., Hybr. and Manuf. Techn., vol. CHMT-7, pp. 193–196 (1984).

    Article  CAS  Google Scholar 

  19. S.K. Tewksbury, et al., Chip alignment templates for multichip module assembly, IEEE Trans. Compon., Hybr. and Manuf. Techn., vol. CHMT-10, pp. 111–121 (1987).

    Article  Google Scholar 

  20. M. Hatamian, S.K. Tewksbury, P. Franzon, L.A. Hornak, C.A. Siller and V.B. Lawrence, FIR filters for high sample rate applications,IEEE Communications, July 1987.

    Google Scholar 

  21. P. Franzon, M. Hatamian, L.A. Hornak, T. Little and S.K. Tewksbury, Fundamental Interconnection Issues, AT&T Techn. J., Aug. 1987.

    Google Scholar 

  22. P. Franzon and S.K. Tewksbury, ’Chip frame’ scheme for reconfigurable mesh connected arrays, Proc. IFIP Workshop on Wafer Scale Integration, Brunel Univ., (Sept. 1987).

    Google Scholar 

  23. J. Grinberg, R.G.R. Mudd and R.D. Etchells, A cellular VLSI architecture, IEEE Computer, pp. 69–81 (Dec. 1984).

    Google Scholar 

  24. A.V. Brown, An overview of Josephson packaging, IBM J. Res. Dev., vol. 24, pp. 167–171 (1980).

    Article  Google Scholar 

  25. J.W. Goodman, Optical interconnects in microelectronics, Proc. SPIE, vol. 456, pp. 72–85 (1984).

    Google Scholar 

  26. J.W. Goodman, F.J. Leonberger, S-Y. Kung and R.A. Athale, Optical interconnections for VLSI systems, Proc. IEEE, vol. 72, pp. 850–866 (1984).

    Article  Google Scholar 

  27. L.A. Hornak and S.K. Tewksbury, On the feasibility of through-wafer optical interconnects for hybrid wafer-scale integrated architectures, IEEE Trans. Elect. Dev., vol. ED-34, pp. 1557–1563 (1987).

    Article  CAS  Google Scholar 

  28. S.R. Forrest, Monolithic optoelectronic integration: a new component technology for lightwave communications, J. Lightwave Technol, vol. LT-3, pp. 1248–1263 (1985).

    Article  Google Scholar 

  29. A. Rosenberg, Three-dimensional VLSI: a case study, J. ACM, vol. 30, pp. 397–416 (1983).

    Article  Google Scholar 

  30. F.P. Preparata, Optimum three dimensional VLSI layouts, Math Systems Theory, vol. 16, pp. 1–8 (1983).

    Article  Google Scholar 

  31. P.H. Hor, et al., Superconductivity above 90K in the square-planar compound system ABa 2 Cu 3 O 6+= with X = Y, La, Sm, Eu, Gd, Ho, Er and Lu, Phys. Rev. Lett., vol. 58, pp. 1891–1894 (1987).

    Article  CAS  Google Scholar 

  32. A. Khurana, Superconductivity seen above the boiling point of nitrogen, Physics Today, vol. 40(4), pp. 17–23 (1987).

    Article  Google Scholar 

  33. J.T. Chen et al., Observation of the reverse ac Josephson effect in Y-Ba-CU-O at 240K Phys. Rev. Lett., vol. 58, pp. 1972–1975 (1987).

    Article  CAS  Google Scholar 

  34. Eds, Superconductivity at room temperature, Nature, vol. 327, pg. 357 (June 4, 1987).

    Google Scholar 

  35. T.R. Gheewala, Josephson-logic devices and circuits, IEEE Trans. Elect. Dev., vol. ED-27, pp. 1857–1869 (1980).

    Article  Google Scholar 

  36. R.L. Kautz, Picosecond pulses on superconducting striplines, J. Appl. Phys, vol. 49, pp. 308–314 (1978).

    Article  CAS  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. AT&T Bell Laboratories, Holmdel, NJ, USA

    S. K. Tewksbury, L. A. Hornak & P. Franzon

Authors
  1. S. K. Tewksbury
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. L. A. Hornak
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. P. Franzon
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. AT&T Bell Laboratories, Holmdel, New Jersey, USA

    Stuart K. Tewksbury

  2. Princeton University, Princeton, New Jersey, USA

    Bradley W. Dickinson  & Stuart C. Schwartz  & 

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Plenum Press, New York

About this chapter

Cite this chapter

Tewksbury, S.K., Hornak, L.A., Franzon, P. (1988). Future Physical Environments and Concurrent Computation. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4684-5511-3_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4684-5513-7

  • Online ISBN: 978-1-4684-5511-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation