Abstract
Three experimental CMOS VLSI circuits implementing connectionist neural network models are discussed in this paper. These chips contain networks of highly interconnected simple processing elements that execute a task distributed over the whole network. A combination of analog and digital computation allows us to build compact circuits so that large networks can be packed on a single chip. Such networks are well-suited for pattern matching and classification tasks, operations that are hard to solve efficiently on a serial architecture.
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© 1988 Plenum Press, New York
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Graf, H.P., Jackel, L.D. (1988). VLSI Implementations of Neural Network Models. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_3
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DOI: https://doi.org/10.1007/978-1-4684-5511-3_3
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