Skip to main content

Partially Augmented Data Manipulator Networks: Minimal Designs and Fault Tolerance

  • Chapter
Concurrent Computations

Abstract

Augmented data manipulator networks are multistage interconnection networks which implement at each stage interconnection functions present in the single stage network known as PM2I network or barrel shifter. These multistage networks include the ADM (Augmented Data Manipulator) and IADM (Inverse Augmented Data Manipulator) networks, which have been extensively studied and proposed for use in multiprocessor systems. This paper derives new partially augmented networks based on the solution to the shortest path problem in the PM2I network. The new networks include: the HADM (Half Augmented Data Manipulator) and HIADM (Half Inverse Augmented Data Manipulator) networks which have half the number of stages of the ADM and IADM networks, the MADM (Minimum Augmented Data Manipulator) and the MIADM (Minimum Inverse Augmented Data Manipulator) networks which have the minimum link complexity required for one-to-one connections in a network of size N with log4 N stages of uniform switches, and the Extra Stage MADM and MIADM networks which are fault-tolerant versions of the MADM and MIADM networks that can tolerate at least three switch failures. The derivations of these networks are presented and their properties and advantages over other designs are analyzed.

This research was supported in part by the National Science Foundation under Grant DC18419745 and by the Innovative Science and Technology Office of the Strategic Defense Initiative Organization and was administered through the Office of Naval Research under contract No. 00014-85-k-0588.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. G. B. Adams III and II. J. Siegel, “The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems,” IEEE Trans. Computers, Vol. C-30, No. 5, pp. 443–454, May 1981.

    Google Scholar 

  2. A. Avizienis, “Signed-Digit Number Representations for Fast Parallel Arithmetic,” IRE Trans. Electronic Computers,pp. 389–400, Sept. 1961

    Google Scholar 

  3. T-Y Feng, “Data Manipulating Functions in Parallel Processors and Their Implementations,” IEEE Trans. Computers, Vol. C-23, No. 3, pp. 309–318, Mar. 1974.

    Article  Google Scholar 

  4. K. Hwang and F. A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill Book Company, NY, pp. 345, 1984.

    Google Scholar 

  5. R. J. McMillen and H. J. Siegel, “Routing Schemes for the Augmented Data Manipulator Network in an MIMD System,” IEEE Trans. Computers, Vol. C-31, No. 12, pp. 1202–1214, Dec. 1982.

    Article  Google Scholar 

  6. D. S. Parker and C. S. Raghavendra, “The Gamma Network: A Multiprocessor Interconnection Network with Redundant Paths,” 9th Annu. Symp. on Computer Architecture, pp. 73–80, Apr. 1982.

    Google Scholar 

  7. D. S. Parker and C. S. Raghavendra, “The Gamma Network,” IEEE Trans. Computers, Vol. C-33, No. 4, pp. 367–373, Apr. 1984.

    Article  Google Scholar 

  8. H. J. Siegel, “Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks,” IEEE Trans. Computer, Vol. C-26, No. 2, pp. 153–161, Feb. 1977.

    Article  Google Scholar 

  9. H. J. Siegel and S. D. Smith, “Study of Multistage SIMD Interconnection Networks,” 5th Annual Symp. on Computer Architecture, pp. 223–229, Apr. 1978.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Plenum Press, New York

About this chapter

Cite this chapter

Rau, D., Fortes, J.A.B. (1988). Partially Augmented Data Manipulator Networks: Minimal Designs and Fault Tolerance. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_27

Download citation

  • DOI: https://doi.org/10.1007/978-1-4684-5511-3_27

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4684-5513-7

  • Online ISBN: 978-1-4684-5511-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics