Abstract
High-performance VLSI processors make extensive use of on-chip cache memories to sustain the memory-bandwidth demands of the CPU. As the amount of chip area devoted to on-chip caches increases, we can expect a substantial portion of the defects/faults to occur in the cache portion of a VLSI processor chip.
This paper studies the tolerance of defects/faults in cache memories. We argue that, even though the major components of a cache are linear RAMs, traditional techniques used for fault/defect tolerance in RAMs may neither be appropriate nor necessary for cache memories. We suggest a scheme that allows a cache to continue operation in the presence of defective/faulty blocks. Then we present the results of a trace-driven simulation analysis that evaluates the performance degradation of a cache due to defective blocks. From the results we see that the on-chip caches of VLSI processors can be organized such that the performance degradation due to a few defective/faulty blocks is negligible. We conclude that by tolerating such defects without a noticeable performance degradation, the yield of VLSI processors can be enhanced considerably.
This work was supported in part by NSF Grant CCR-8706722.
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© 1989 Plenum Press, New York
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Sohi, G.S. (1989). Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_19
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DOI: https://doi.org/10.1007/978-1-4615-6799-8_19
Publisher Name: Springer, Boston, MA
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