Abstract
We present a comparison-based algorithm for identifying faulty and fault-free elements in a wafer-scale linear array of processors (or other logic elements). Only nearest neighbor communication is assumed to be possible between the processors in the array. Because the algorithm is simple and requires no storage of test vectors or test outcomes, it is ideally suited for implementation on the wafer to provide the capability for built-in production (or post production) testing. We show that surprisingly this algorithm achieves high accuracy of diagnosis over a wide range of yields even though the diagnosis may be based on a high proportion of results produced by faulty processors. Quantitative and qualitative reasoning validate the efficiency of the algorithm.
This research was supported in part by the Office of Naval Research under Contracts N00014-86-K-0597 and N00014-86-K-0763.
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© 1989 Plenum Press, New York
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Fussell, D., Rangarajan, S., Malek, M. (1989). Fault Diagnosis of Linear Processor Arrays. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_14
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DOI: https://doi.org/10.1007/978-1-4615-6799-8_14
Publisher Name: Springer, Boston, MA
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