Abstract
With the growing complexity of semiconductor processing technologies, the ability to predict the manufacturing yield of an integrated circuit at the design stage has become increasingly important. This allows the designer to evaluate the feasibility of a particular design from an economical point of view, and to optimize the partitioning of a system into individual ICs. The yield projection methodology described here has the added capability of distinguishing the contribution of each failure mode to the total yield loss. This is a valuable feature for fault-tolerant circuit design and the development of efficient high fault coverage test programs.
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© 1989 Plenum Press, New York
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Schvan, P., Montuno, D.Y., Hadaway, R. (1989). Yield Projection Based on Electrical Fault Distribution and Critical Structure Analysis. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_11
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DOI: https://doi.org/10.1007/978-1-4615-6799-8_11
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4615-6801-8
Online ISBN: 978-1-4615-6799-8
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