Abstract
For power to be used as a design parameter, tools are needed that can efficiently estimate the power consumption of a given design. As in most engineering problems we have tradeoffs, in this case between the accuracy and run-time of the tool.
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References
R. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C-35(8):677–691, August 1986.
R. Burch, F. Najm, P. Yang, and T. Trick. A Monte Carlo Approach to Power Estimation. IEEE Transactions on VLSI Systems, 1(1):63–71, March 1993.
A. Chandrakasan, T. Sheng, and R. Brodersen. Low Power CMOS Digital Design. Journal of Solid State Circuits, 27(4):473–484, April 1992.
D. Cheng. Power Estimation of Digital CMOS Circuits and the Application to Logic Synthesis for Low Power. PhD thesis, University of California at Santa Barbara, December 1995.
M. Cirit. Estimating Dynamic Power Consumption of CMOS Circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 534–537, November 1987.
S. Devadas, K. Keutzer, and J. White. Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation. IEEE Transactions on Computer-Aided Design, 11(3):373–383, March 1992.
S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco. Testability Measures in Pseudo-Random Testing. IEEE Transactions on Computer-Aided Design, 11(6):794–799, June 1992.
M. Favalli and L. Benini. Analysis of Glitch Power Dissipation in CMOS ICs. In Proceedings of the International Symposium on Low Power Design, pages 123–128, April 1995.
H. Goldstein. Controllability/Observability of Digital Circuits. IEEE Transactions on Circuits and Systems, 26(9):685–693, September 1979.
A. Hill and S. Kang. Determining Accuracy Bounds for Simulation-Based Switching Activity Estimation. In Proceedings of the International Symposium on Low Power Design, pages 215–220, April 1995.
B. Kapoor. Improving the Accuracy of Circuit Activity Measurement. In Proceedings of the International Workshop on Low Power Design, pages 111–116, April 1994.
B. Krishnamurthy and I. G. Tollis. Improved Techniques for Estimating Signal Probabilities. IEEE Transactions on Computers, 38(7):1041–1045, July 1989.
S. Manne, A. Pardo, R. Bahar, G. Hachtel, F. Somenzi, E. Macii, and M. Poncino. Computing the Maximum Power Cycles of a Sequential Circuit. In Proceedings of the 32nd Design Automation Conference, pages 23–28, June 1995.
F. Najm. Transition Density: A New Measure of Activity in Digital Circuits. IEEE Transactions on Computer-Aided Design, 12(2):310–323, February 1993.
F. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits. IEEE Transactions on Computer-Aided Design, 9(4):439–450, April 1990.
A. Papoulis. Probability, Random Variables and Stochastic Processes. McGraw-Hill, 3rd edition, 1991.
K. Parker and E. McCluskey. Probabilistic Treatment of General Combinational Networks. IEEE Transactions on Electronic Computers, C-24(6):668–670, 1975.
T. Quarles. The SPICE3 Implementation Guide. Technical Report ERL M89/44, Electronics Research Laboratory Report, University of California at Berkeley, Berkeley, California, April 1989.
A. Salz and M. Horowitz. IRSIM: An Incremental MOS Switch-Level Simulator. In Proceedings of the 26th Design Automation Conference, pages 173–178, June 1989.
A. Shen, S. Devadas, A. Ghosh, and K. Keutzer. On Average Power Dissipation and Random Pattern Testability of Combinational Logic Circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 402–407, November 1992.
R. Tjarnstrom. Power Dissipation Estimate by Switch Level Simulation. In Proceedings of the International Symposium on Circuits and Systems, pages 881–884, May 1989.
C-Y. Tsui, M. Pedram, and A. Despain. Efficient Estimation of Dynamic Power Dissipation under a Real Delay Model. In Proceedings of the International Conference on Computer-Aided Design, pages 224–228, November 1993.
T. Uchino, F. Minami, T. Mitsuhashi, and N. Goto. Switching Activity Analysis using Boolean Approximation Method. In Proceedings of the International Conference on Computer-Aided Design, pages 20–25, November 1995.
N. Weste and K. Eshraghian. Principles of CMOS VLSI Design. Addison-Wesley Publishing Company, second edition, 1994.
M. Xakellis and F. Najm. Statistical Estimation of the Switching Activity in Digital Circuits. In Proceedings of the 31st Design Automation Conference, pages 728–733, June 1994.
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© 1997 Springer Science+Business Media New York
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Monteiro, J., Devadas, S. (1997). Power Estimation. In: Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. The Springer International Series in Engineering and Computer Science, vol 387. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6319-8_2
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DOI: https://doi.org/10.1007/978-1-4615-6319-8_2
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