Development and Implementation of Robust and Spectrally Efficient Medium Data Rate Modems Part 1: Architectures

Abstract

Currently, the ITR is near completion of the second phase of a project which involves the design and prototyping of a medium data rate modem (2–16 Mbit/s) applicable to both microwave line of sight and satellite communications systems. The designs of both the modulator and demodulator are novel at these rates as the architectures are based on IF sampling techniques as opposed to traditional baseband I/Q approaches [1]. This technique of sampling wanted signals at IF has gained prominence in the design of PCS mobile radio receivers which typically involves signal bandwidths which are much less than those dealt within this system. Low-IF approaches to both modulation and demodulation offer performance advantages as a consequence of moving the digital/analog interface in favour of more digital signal processing. This however requires relatively high computational load and puts the implementation of wideband modems beyond the capabilities of programmable digital signal processors. Hence architectures based upon FPGA technology and look up tables (LUT’s) have been developed to satisfy the requirement. In Section 2 the principle of low-IF modulation is briefly discussed and the design of the low-IF modulator is presented together with a discussion of design considerations and an example of a generated spectrum. In Section 3, bandpass sampling is discussed and the design of the demodulator is presented together with a discussion of its unique design considerations. In Section 4 the modem measured performance is presented and in Section 5 the advantages of the system Reed-Solomon coding option are illustrated together with a brief discussion of the codec implementation. In Section 6 the third phase of the project which involves the extension of the design to support a data rate of 34.4 Mbit/s is discussed from an implementation perspective.