A Detailed Analysis of Phase Locked Loops Used in Clock Jitter Reduction

Abstract

In digital communication systems, it is often necessary to derive smoothed data clocks from incoming jittered data clocks. As an example, the gapped clock resulting from pulse stuffing and pointer processing in add/drop multiplexer nodes of synchronous digital hierarchy (SDH) networks is such a jittered clock. Typically, a Phase Locked Loop (PLL) is used for the recovery of a smoothed data clock from the jittered clock. The PLL filter is designed such that the deviations of the recovered clock from an ideal (jitter free) data clock are within the allowable limits. The performance of the PLLs in filtering continuous time signals is very well known. Using approximations, it is often customary to extend this continuous time signal analysis to discrete time systems (e.g. systems associated with clock signals) [1]. However, the details and the validity of such approximations are not adequately addressed in the open literature.