Abstract
In a previous paper presented at the 1994 International Symposium on DSP for Communication Systems [1] we described the problem of pipelining feedback systems such as IIR digital filters for high-speed communication systems. The throughput speed appears at first to be constrained in a fundamental way by delays through multipliers in the feedback loops. As shown by Messerschmitt and others, however, this problem is not, in fact, a fundamental one: but can be circumvented by use of the “Messerschmitt transformation”, in which a multiply-iterated version of the system equation is used as the basis of the implementation, rather than the original uniterated equation.
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References
N. Burgess and K. V. Lever: “New High-Speed VLSI Filter Architectures using Regular Arrays of Pipelined Variable-Delay Multiplier Accumulators”, Proc. of the 2nd International Symposium on DSP for Communication Systems (DSPCS’94), Adelaide, 26–29 April 1994.
K. K. Parhi and D. G. Messerschmitt: “Pipeline Interleaving and Parallelism in Recursive Digital Filters — Part I: Pipelining Using Scattered Look-Ahead and Decomposition”, IEEE Trans. on Acoustics, Speech and Signal Processing, Vol. 37, No. 7, July 1989, pp. 1099–1117.
K.V. Lever, F.M. Clayton and G.J. Janacek: “Minimisation of Architectural Complexity in the Design of Adaptive Equalisers for Digital Radio Systems”, In Mathematical Modelling for Information Technology, Ed. A.O. Moscardini and E.H. Robson, Ellis Horwood 1988, pp. 60–78.
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© 1997 Springer Science+Business Media New York
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Phillips, B.J., Burgess, N., Lever, K.V. (1997). Regularisation Procedures for Iterated Recursive Digital Filters. In: Wysocki, T., Razavi, H., Honary, B. (eds) Digital Signal Processing for Communication Systems. The Springer International Series in Engineering and Computer Science, vol 403. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6119-4_24
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DOI: https://doi.org/10.1007/978-1-4615-6119-4_24
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