Skip to main content

Abstract

Closed form expressions are presented to accurately describe the delay characteristics of RC tree networks. The Penfield-Rubinstein-Horowitz approach to estimating the step function response of RC trees has been extended to consider ramp inputs. This result improves timing accuracy by considering the shape of the input waveform driving each individual interconnect tree while maintaining computational simplicity for use in the automated timing analysis of complex VLSI circuits.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. P. Penfield, Jr., and J. Rubinstein, “Signal delay in RC tree networks.” Proceedings of Caltech Conference on VLSI, pp. 269–283, January 1981.

    Google Scholar 

  2. J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Transactions on Computer-Aided Design, CAD-2(3), pp. 202–211, July 1983.

    Google Scholar 

  3. A. B. Kahng and S. Muddu, “Analysis of RC interconnections under ramp input,” Proceedings of the ACM/IEEE Design Automation Conference, 4pp. 533–538, June 1996.

    Google Scholar 

  4. E. G. Friedman and J. H. Mulligan, Jr., “Ramp input response of RC tree network,” Proceedings of the IEEE ASIC Conference,11 pp. 63–66, September 1996.

    Google Scholar 

  5. M. A. Horowitz, “Timing models of MOS circuits,” Technical Report No. SEL 83–003, Integrated Circuits Laboratory, Stanford University, Stanford, California, December 1983.

    Google Scholar 

  6. J. L. Wyatt, Jr., “Waveform bounding for fast timing analysis of MOS VLSI circuits,”Proceedings of IEEE International Symposium on Circuits and Systems,4 pp. 760–761, May 1983.

    Google Scholar 

  7. J. L. Wyatt, Jr., and Q. Yu, “Signal delay in RC meshes, trees and lines,” Proceedings of the IEEE International Conference on Computer-Aided Design,21 pp. 15–17, November 1984.

    Google Scholar 

  8. Q. Yu, J. L. Wyatt, Jr., C. Zukowski, H-N. Tan, and P. O’Brien, “Improved bounds on signal delay in linear RC models for MOS interconnect,” Proceedings of the IEEE International Symposium on Circuits and Systems, 7pp. 903–906, June 1985.

    Google Scholar 

  9. J. L. Wyatt, Jr., “Signal delay in RC mesh networks,” IEEE Transactions on Circuits and Systems, CAS-32(5), pp. 507–510, May 1985.

    Article  Google Scholar 

  10. J. L. Wyatt, Jr., “Signal propagation delay in RC models for interconnect,” Circuit Analysis, Simulation andDesign, Part II: VLSI Circuit Analysis and Simulation, A. Ruehli, ed., Vol. 3 in the series Advances in CAD for VLSI, North-Holland, 1987.

    Google Scholar 

  11. D. Standley and J. L. Wyatt, Jr., “Improved signal delay bounds for RC tree networks,” VLSI Memo No. 86–317, Massachusetts Institute of Technology, Cambridge, Massachusetts, May 1986.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 1997 Springer Science+Business Media New York

About this chapter

Cite this chapter

Friedman, E.G., Mulligan, J.H. (1997). Ramp Input Response of RC Tree Networks. In: Becerra, J.J., Friedman, E.G. (eds) Analog Design Issues in Digital VLSI Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6101-9_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-6101-9_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-7795-5

  • Online ISBN: 978-1-4615-6101-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics