Abstract
A delay and power model of a CMOS inverter driving a resistive-capacitive load is presented. The model is derived from Sakurai’s alpha-power law and exhibits good accuracy. The model can be used to design and analyze those CMOS inverters that drive a large RC load when considering both speed and power. Expressions are provided for estimating the propagation delay and transition time which exhibit less than 27% discrepancy from SPICE for a wide variety of RC loads. Expressions are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a resistive-capacitive interconnect line which are accurate to within 15% of SPICE for most practical loads.
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Adler, V., Friedman, E.G. (1997). Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load. In: Becerra, J.J., Friedman, E.G. (eds) Analog Design Issues in Digital VLSI Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6101-9_3
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DOI: https://doi.org/10.1007/978-1-4615-6101-9_3
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