Abstract
Today, the most common abstraction level for manual design capture is at the so called register transfer level. At this level, all synchronous registers, latches and the combinational logic between the sequential elements are described in a hardware description language such as Verilog or VHDL. The description is then transformed into logic gate implementations based on a technology specific cell library, a procedure known as logic synthesis. This allows a designer to handle more complex design because detailed manual analysis need not be made at the logic gate level that is more tedious and error prone. Register transfer level is certainly not the only starting point for automated hardware synthesis. The analysis and synthesis of digital circuits are still being pushed toward even higher level of abstraction for manual manipulation. For example, macro block level specification and synthesis has been practiced in some design areas. The register transfer and macro block level design methodologies are part of the architecture and system level techniques to be discussed in this chapter.
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References
A. Chandrakasan, S. Sheng and R. Brodersen, “Low-power CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473–484, Apr. 1992.
G. Gerosa, et al., “A 2.2 Watt 80 MHz Superscalar RISC Microprocessor,” IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1440–1454, Dec.1996.
L. Nielsen, C. Niessen, J. Sparso and K. van Berkel, “Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage,” IEEE Transactions on VLSI Systems, vol. 2, no. 4, pp. 391–397, Dec. 1994.
K. Usami and M. Horowitz, “Clustered Voltage Scaling Technique for Low-Power Design,” Proceedings of International Symposium on Low Power Design, pp. 3–8, 1995.
K. Usami, et al., “Automated Low-power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor,” Proceedings of Custom Integrated Circuit Conference, pp. 131–134, 1997.
J. Ludwig, S. Nawab and A. Chandrakasan, “Low-Power Digital Filtering Using Approximate Processing,” IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp. 395–400, Mar. 1996.
V. Tiwari, S. Malik and P. Ashar, “Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design,” Proceedings of International Symposium on Low Power Design, pp. 221–226, 1995.
A. Chandrakasan, M. Potkonjak, J. Rabaey and R. Brodersen, “HYPER-LP: A system for Power Minimization using Architectural Transformations,” Proceedings of International Conference of Computer-Aided Design, pp. 300–303, 1992.
A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabey and R. Brodersen, “Optimizing Power Using Transformations,” IEEE Transactions on Computer Aided Design, vol. 14, no. 1, pp. 12–31, Jan. 1995.
M. Potkonjak, M. Srivastava and A. Chandrakasan, “Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions using Iterative Pairwise Matching,” Proceedings of Design Automation Conference, pp. 189–194, 1996.
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© 1998 Springer Science+Business Media New York
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Yeap, G. (1998). Architecture and System. In: Practical Low Power Digital VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6065-4_7
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DOI: https://doi.org/10.1007/978-1-4615-6065-4_7
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