Trellis Sectionalization

Abstract

So far, we have only considered bit-level N-section trellis diagrams for linear block codes of length N. In a bit-level trellis diagram, every time instant in the encoding interval Γ = 0,1,2,…, N is a section boundary location and every branch represents a code bit. It is possible to sectionalize a bit-level trellis with section boundary locations at selected instants in the encoding interval Γ. This sectionalization results in a trellis in which a branch may represent multiple code bits and two adjacent states may be connected by multiple branches. Proper sectionalization may result in useful trellis structural properties and allow us to devise efficient trellis-based decoding algorithms. This chapter is devoted in analyzing sectionalized trellis diagrams for linear block codes. Section 6.1 presents the concepts and rules for trellis sectionalization. In Section 6.2, the branch complexity and state connectivity are analyzed and expressed in terms of the dimensions of codes related to the code being considered. In Section 6.3, construction of a sectionalized trellis diagram for a linear block code based on the trellis oriented generator matrix is presented. Section 6.4 studies the parallel structure of a sectionalized trellis diagram.