Skip to main content

Test Generation for Path Delay Faults

  • Chapter
Delay Fault Testing for VLSI Circuits

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 14))

  • 216 Accesses

Abstract

This chapter concentrates on multi-value systems and methods proposed for generating tests for single and multiple path delay faults. The robust, non-robust, validatable non-robust and functional sensitizable faults are considered as single path delay faults. These paths usually can be tested with many different tests, i.e., there are many different robust tests for a robust testable path, many different non-robust tests for a non-robust testable path, etc. Since robust tests are guaranteed to detect a faulty target path independent of whether or not there are delay faults on paths other than the target path, most test generators do not differentiate between robust tests for a given path. These test generators do not use any timing information. On the other hand, some non-robust tests have a higher probability of detecting a faulty non-robust testable path than other tests. Similar argument holds for the functional sensitizable tests. The higher quality non-robust and functional sensitizable tests can be found by including the timing information into the test generation process. This chapter presents test generation algorithms that can produce high quality tests based on using the timing information for the non-robust and functional sensitizable faults. A non-robust test for a given target path becomes invalid if certain other paths in the circuit are defective. If the faults that may invalidate the non-robust test for the target path can be robustly tested, those robust tests along with the non-robust test for the target path form a validatable non-robust test (VNR). An algorithm for automatic generation of validatable non-robust tests is outlined in this chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 1998 Springer Science+Business Media New York

About this chapter

Cite this chapter

Krstić, A., Cheng, KT. (1998). Test Generation for Path Delay Faults. In: Delay Fault Testing for VLSI Circuits. Frontiers in Electronic Testing, vol 14. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5597-1_7

Download citation

  • DOI: https://doi.org/10.1007/978-1-4615-5597-1_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-7561-6

  • Online ISBN: 978-1-4615-5597-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics